A semiconductor EEPROM device and a method for making it are achieved. The EEPROM device is a novel twin-bit cell structure with adjacent floating gates having a common control gate and common bit-line contact in each cell area. In each cell area a first and second floating gate is formed. Source areas are formed in the substrate adjacent to the outer edges of the floating gates and a drain area is formed between and adjacent to the floating gates. A gate oxide is formed over the floating gates. A control gate is formed over the drain area and patterned to also partially extend over the floating gates. The control gate is also patterned to provide a recess for a bit-line contact to the drain area. The recess results in reduced cell area and the non-critical overlay of the control gate over the floating gates results in relaxed overlay alignment.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of fabricating an array of non-volatile memory cells for EEPROM circuits comprising the steps of: providing a substrate having an array of device areas; forming a tunnel oxide layer on said array of device areas; forming a first and second floating gate in each device area of said array of device areas; forming source areas in said substrate adjacent to outer edge of said floating gates and forming a drain area adjacent to and between said first and second floating gates; forming a gate oxide layer on said floating gates; forming a control gate over said drain area, and extending over said first and second floating gates, said control gate patterned with recesses to expose underlying portions of said drain area for a bit line contact; forming an interlevel dielectric layer on said substrate; etching a contact opening in said interlevel dielectric layer to said drain area for said bit line contact in each said device area in said array of device areas.
2. The method of claim 1 , wherein said tunnel oxide is silicon oxide and is formed by thermal oxidation.
3. The method of claim 1 , wherein said tunnel oxide is formed to a thickness of about 40 to 250 Angstroms.
4. The method of claim 1 , wherein said first and second floating gates are formed from a polysilicon layer deposited to a thickness of about 300 to 3000 Angstroms and doped to a concentration of between about 1.0 E 19 and 1.0 E 21 atoms/cm 3 .
5. The method of claim 1 , wherein said source areas and said drain area are formed by ion implanting a conductive dopant in said device areas.
6. The method of claim 5 , wherein said conductive dopant is N type having a final concentration of between about 1.0 E 18 and 1.0 E 20 atoms/cm 3 in said source areas and said drain area.
7. The method of claim 1 , wherein said gate oxide is silicon oxide formed by thermal oxidation to a thickness of about 20 to 1000 Angstroms.
8. The method of claim 1 , wherein said control gate is formed from a polysilicon layer that has a thickness of between about 300 and 5000 Angstroms and is doped to a concentration of between about 1.0 E 19 and 1.0 E 21 atoms/cm 3 .
9. The method of claim 1 , wherein said interlevel dielectric layer is borophosphosilicate glass and is deposited by low-pressure chemical vapor deposition to a thickness of between about 2000 to 8000 Angstroms.
10. The method of claim 1 , wherein said contact opening is etched using high-density plasma etching and an etchant gas that contains fluorine.
11. A method of fabricating an array of non-volatile memory cells for EEPROM circuits comprising the steps of: providing a substrate having an array of device areas; forming a tunnel oxide layer on said array of device areas; forming a first and second floating gate in each device area of said array of device areas; forming source areas in said substrate adjacent to outer edge of said floating gates and forming a drain area adjacent to and between said first and second floating gates; forming a gate oxide layer on said floating gates; forming a control gate over said drain area, and partially extending over said first and second floating gates, said control gate patterned with recesses to expose underlying portions of said drain area for a bit line contact; forming an interlevel dielectric layer on said substrate; etching a contact opening in said interlevel dielectric layer to said drain area for said bit line contact in each said device area in said array of device areas.
12. The method of claim 11 , wherein said tunnel oxide is silicon oxide and is formed by thermal oxidation.
13. The method of claim 11 , wherein said tunnel oxide is formed to a thickness of about 40 to 250 Angstroms.
14. The method of claim 11 , wherein said first and second floating gates are formed from a polysilicon layer deposited to a thickness of about 300 to 3000 Angstroms and doped to a concentration of between about 1.0 E 19 and 1.0 E 21 atoms/cm 3 .
15. The method of claim 11 , wherein said source areas and said drain area are formed by ion implanting a conductive dopant in said device areas.
16. The method of claim 15 , wherein said conductive dopant is N type having a final concentration of between about 1.0 E 18 and 1.0 E 20 atoms/cm 3 in said source areas and said drain area.
17. The method of claim 11 , wherein said gate oxide is silicon oxide formed by thermal oxidation to a thickness of about 20 to 1000 Angstroms.
18. The method of claim 11 , wherein said control gate is formed from a polysilicon layer that has a thickness of between about 300 and 5000 Angstroms and is doped to a concentration of between about 1.0 E 19 and 1.0 E 21 atoms/cm 3 .
19. The method of claim 11 , wherein said interlevel dielectric layer is borophosphosilicate glass and is deposited by low-pressure chemical vapor deposition to a thickness of between about 2000 to 8000 Angstroms.
20. The method of claim 11 , wherein said contact opening is etched using high-density plasma etching and an etchant gas that contains fluorine.
21. An array of non-volatile memory cells for EEPROM circuits comprised of: a substrate having an array of device areas; a tunnel oxide layer on said array of device areas; a first and second floating gate in each device area of said array of device areas; source areas in said substrate adjacent to outer edge of said floating gates and a drain area adjacent to and between said first and second floating gates; a gate oxide layer on said floating gates; a control gate over said drain area partially extending over said first and second floating gates, said control gate patterned with recesses to expose underlying portions of said drain area for a bit line contact; an interlevel dielectric layer on said substrate; a contact opening in said interlevel dielectric layer to said drain area for said bit line contact in each said device area in said array of device areas.
22. The structure of claim 21 , wherein said tunnel oxide is silicon oxide and has a thickness of about 40 to 250 Angstroms.
23. The structure of claim 21 , wherein said first and second floating gates are formed from a polysilicon layer doped to a concentration of between about 1.0 E 19 and 1.0 E 21 atoms/cm 3 .
24. The structure of claim 21 , wherein said gate oxide is silicon oxide and has a thickness of about 20 to 1000 Angstroms.
25. The structure of claim 21 , wherein said control gate is polysilicon that has a thickness of between about 300 and 5000 Angstroms and is doped to a concentration of between about 1.0 E 19 and 1.0 E 21 atoms/cm 3 .
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 4, 2001
September 16, 2003
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