A transistor (50) comprising a gate conductor (68) and a gate insulator (66) separating the gate conductor from a semiconductor material (64) having a first conductivity type. The transistor further comprises a drain region (782) having the first conductivity type. The transistor further comprises an angular implanted region (70) having a second conductivity type complementary of the first conductivity type and having an angular implanted region edge (70a) underlying the gate conductor, and the transistor includes a source region (781) formed at least in part within the angular implanted region. Finally, a transistor channel (74) is defined between an edge (71a) of the source region proximate the gate conductor and the angular implanted region edge (70a) underlying the gate conductor.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of forming an integrated circuit, comprising the steps of: forming a gate insulator; forming a gate conductor relative to the gate insulator such that the gate insulator separates the gate conductor from a semiconductor material having a first conductivity type; forming a drain region having the first conductivity type; performing an angular implant to form an angular implanted region having a second conductivity type complementary of the first conductivity type and having an angular implanted region edge underlying the gate conductor; forming a source region formed within the angular implanted region; and wherein the steps of performing an angular implant and forming a source region define a transistor channel between an edge of the source region proximate the gate conductor and the angular implanted region edge underlying the gate conductor.
2. The method of claim 1 wherein the edge of the source region proximate the gate conductor is self-aligned with respect to the gate conductor.
3. The method of claim 2 wherein the angular implanted region edge underlying the gate conductor is self-aligned with respect to the gate conductor.
4. The method of claim 3 wherein the semiconductor material having a first conductivity type comprises a semiconductor material having an n-type.
5. The method of claim 4 wherein the semiconductor material comprises an n-well formed in a p-type semiconductor substrate.
6. The method of claim 5 and further comprising: forming a gate insulator separating at least a portion of the gate conductor from the semiconductor material; and forming an insulating region proximate one edge of the gate conductor; and wherein the drain region has a first edge abutting the insulating region and a second edge extending away from the insulating region and the gate conductor.
7. The method of claim 6 wherein the drain region has a higher dopant concentration than the semiconductor material.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 26, 2002
September 16, 2003
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