A delay line receives an input clock signal and includes a cascaded plurality of unit delay circuits. A mode register set stores a value indicative of a column-address-strobe (CAS) latency of the memory device, and an adjustment circuit varies a delay time of the unit delay circuits according to the CAS latency stored in the mode register set. A phase detector detects a phase difference between the input clock signal and an output clock signal of the delay line, and a control circuit which controls an enabled state of the unit delay circuits according to an output of said phase detector.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A delay locked loop circuit for a memory device, comprising: a delay line which receives an input clock signal and which includes a cascaded plurality of unit delay circuits; an adjustment circuit which varies a delay time of said unit delay circuits according to a column-address-strobe (CAS) latency of the memory device; a phase detector which detects a phase difference between the input clock signal and an output clock signal of said delay line; and a control circuit which controls an enabled state of said unit delay circuits according to an output of said phase detector.
2. The delay locked loop circuit of claim 1 , further comprising a mode register set for outputting a signal indicative of the CAS latency to said adjustment circuit.
3. The delay locked loop circuit of claim 2 , wherein said adjustment circuit comprises a plurality of variable delay circuits coupled to said unit delay circuits, respectively, wherein each of said variable delay circuits is responsive to the signal output from said mode register set to control an amount of delay of a respective unit delay circuit.
4. The delay locked loop circuit of claim 3 , wherein each of said variable delay circuits comprises plural circuits connected in parallel between a source voltage and a respective unit delay circuit, each said circuit comprising a capacitor and a switch connected in series, wherein an ON/OFF state of said switch of each of said plural circuits is controlled by the output of said mode register set.
5. The delay locked loop circuit of claim 4 , wherein the capacitor of each said circuit is an NMOS capacitor and the source voltage is a ground voltage.
6. The delay locked loop circuit of claim 3 , wherein the capacitor of each said circuit is a PMOS capacitor and the source voltage is a power voltage.
7. The delay locked loop circuit of claim 3 , wherein said adjustment circuit further comprises: a logic circuit, having plural output terminals, for generating respective logic values on the plural output terminals in response to the signal output from said mode register set; wherein each of said variable delay circuits comprises plural capacitors which are each connected in parallel between a respective unit delay circuit and a respective one of said plural output terminals of said logic circuit.
8. The delay locked loop circuit of claim 1 , wherein said unit delay circuits are digital circuits, wherein said control circuit comprises a shift register circuit which outputs parallel control signals to said unit delay circuits, respectively, and wherein a bit-shift direction of said shift register circuit is controlled by the output of said phase detector.
9. The delay locked loop circuit of claim 4 , wherein said unit delay circuits are digital circuits, wherein said control circuit comprises a shift register circuit which outputs parallel control signals to said unit delay circuits, respectively, and wherein a bit-shift direction of said shift register circuit is controlled by the output of said phase detector.
10. The delay locked loop circuit of claim 7 , wherein said unit delay circuits are digital circuits, wherein said control circuit comprises a shift register circuit which outputs parallel control signals to said unit delay circuits, respectively, and wherein a bit-shift direction of said shift register circuit is controlled by the output of said phase detector.
11. The delay locked loop circuit of claim 1 , wherein said unit delay circuits are analog circuits, wherein said control circuit comprises a charge pump and a low pass filter, wherein an output of said low pass filter is commonly connected to said unit delay circuits, and wherein a charge direction of said charge pump is controlled by an output of said phase detector.
12. The delay locked loop circuit of claim 4 , wherein said unit delay circuits are analog circuits, wherein said control circuit comprises a charge pump and a low pass filter, wherein an output of said low pass filter is commonly connected to said unit delay circuits, and wherein a charge direction of said charge pump is controlled by an output of said phase detector.
13. The delay locked loop circuit of claim 7 , wherein said unit delay circuits are analog circuits, wherein said control circuit comprises a charge pump and a low pass filter, wherein an output of said low pass filter is commonly connected to said unit delay circuits, and wherein a charge direction of said charge pump is controlled by an output of said phase detector.
14. The delay locked loop circuit of claim 1 , further comprising a delay compensation circuit interposed between the output of said delay line and an input of said phase detector, wherein said phase detector detects the phase difference between the input clock signal and the output clock signal of said delay line after the output clock signal is delayed by said delay compensation circuit.
15. A delay locked loop method for a memory device, comprising: delaying an input clock signal to obtain a delayed clock signal by passing the input clock signal through a delay line having a cascaded plurality of unit delay circuits; controlling an enabled state of each of the unit delay circuits according to a phase difference between the input clock signal and the delayed clock signal; and varying a delay time of the unit delay circuits according to a column-address-strobe (CAS) latency of the memory device.
16. The delay locked loop method of claim 15 , wherein the delay time of the unit delay circuits is increased as the CAS latency of the memory device is decreased.
17. The delay locked loop method of claim 15 , wherein the delay time of the unit delay circuits is varied by altering a capacitive load operatively connected to the unit delay circuits.
18. The delay locked loop method of claim 15 , further comprising storing a value indicative of the CAS latency of the memory device, and controlling an on/off state of plural switched capacitor circuits according to the stored value indicative of the CAS latency, wherein the switched capacitor circuits are operatively connected to the unit delay circuits, respectively.
19. A delay locked loop circuit for a memory device, comprising: a delay line which receives an input clock signal and which includes a cascaded plurality of unit delay circuits; a shift register circuit having plural circuit stages which output parallel control signals to said unit delay circuits, respectively, wherein said parallel control signals constitute a multi-bit output of said shift register circuit, wherein the number of stages of each bit-shift operation of said shift register circuit is controlled by a column address strobe (CAS) latency of the memory device, and wherein a direction and a number of stages of the bit-shift operation of said shift register circuit are variable; and a phase detector for detecting a phase difference between the input clock signal and an output clock signal of said delay line, wherein the direction of the bit-shift operation of said shift register circuit is controlled by an output of said phase detector.
20. The delay locked loop circuit of claim 19 , further comprising a mode register set which stores a value indicative of the CAS latency.
21. The delay locked loop circuit of claim 20 , wherein said shift register circuit comprises: plural flip-flop circuit stages; and a plurality of switching circuits which selectively enable said plural flip-flop circuit stages during the bit-shift operation according to the value stored in said mode register set.
22. The delay locked loop circuit of claim 20 , wherein the shift register circuit comprises: first, second and third flip-flop circuits; a first switch connected in series between an output node of the first flip-flop circuit and an output node of the third flip-flop circuit; a second switch connected in series between the output node of the first flip-flop circuit and an input node of the third flip-flop circuit; a third switch connected in series between the output node of the first flip-flop circuit and an input node of the second flip-flop circuit; and a fourth switch connected in series between an output node of the second flip-flop circuit and the input node of the third flip-flop circuit.
23. The delay locked loop circuit of claim 22 , wherein an output of said mode register set controls an ON/OFF state of each of said first through fourth switches.
24. The delay locked loop circuit of claim 23 , wherein the first switch is closed and the second through fourth switches are open when a number of stages of each bit-shift operation is three, wherein the second switch is closed and the first, third and fourth switches are open when a number of stages of each shift operation is two, and wherein the third and fourth switches are closed and the first and second switches are open when the number of stages of each shift operation is one.
25. The delay locked loop circuit of claim 19 , further comprising a delay compensation circuit interposed between the output of said delay line and an input of said phase detector detects the phase difference between the input clock signal and the output clock signal of said delay line after output clock signal is delayed by said delay compensation circuit.
26. A delay locked loop method for a memory device, comprising: delaying an input clock signal to obtain a delayed clock signal by passing the input clock signal through a delay line having a cascaded plurality of unit delay circuits; generating a multi-bit control signal which controls an enabled state of each of the plurality of unit delay circuits; and bit-shifting the multi-bit control signal in a direction corresponding to a phase difference between the input clock signal and the delayed clock signal, and by a number of bits corresponding to a column address strobe (CAS) latency of the memory device.
27. The delay locked loop method of claim 26 , wherein the number of bits of the bit-shifting of the multi-bit control signal is increased as the CAS latency of the memory device is decreased.
28. The delay locked loop method of claim 26 , further comprising storing a value indicative of the CAS latency of the memory device, and controlling an enabled state of plural shift register stages according to the stored value indicative of the CAS latency, wherein the plural shift register stages generate the multi-bit control signal.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 1, 2002
September 16, 2003
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