A computer for data processing and a method for data processing using a computer, each of which is used for reversing, with the aid of a circuit arrangement, the bit sequence of the information, which was coded with a reversible Huffman code, when an error occurs, so that the computer decodes the reversed bit sequences using a suitable code table. In the computer, a data buffer is connected to a register in such a way that the bit sequence is reversed when transferred from the data buffer to the register. The bit sequence is not reversed when it is retransferred from the register into the data buffer. In this way, information which is located after the error does not get lost. Since to reverse the bit sequence, the end of the bit sequence, designated by a synchronization bit sequence, must be found, the synchronization bit sequence is disposed at byte boundaries due to padding bits. In this way, synchronization bit sequences are located only at byte boundaries. Since the computer must load code tables for the decoding, various reversible and non-reversible codes can be used. The computer recognizes the beginning of a group of coded information on the basis of the synchronization bit sequence.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A computer for processing data, the data being generated with a reversible code and including bit sequences having various lengths, the computer comprising: memory; a register; a data buffer coupled to the register so that a bit sequence of data transmitted from the data buffer to the register is reversed, the register being coupled to the data buffer so that a bit sequence of data transmitted from the register to the data buffer is maintained, wherein a group of data is enclosed by synchronization bit sequences; and at least one arrangement that performs the steps of: transferring the data of a group from the data buffer into the register when an erroneous bit is recognized in a bit sequence of the data of the group, retransferring the data from the register into the data buffer, the data being retransfered so that the bits in the data buffer have the same sequence as in the register, and comparing and decoding bit sequences up to the erroneous bit using stored bit sequences for decoding bit sequences having bits in reversed sequence.
2. The computer according to claim 1 , wherein: the reversible code includes the Huffman code.
3. The computer according to claim 1 , wherein: the computer performs the further step of changing the group of data enclosed by the synchronization bit sequences to a word-oriented bit length using padding bits.
4. The computer according to claim 3 , wherein: the computer performs the further step of loading known bit sequences for decoding of data in the memory, the data being coded with one of reversible codes and non-reversible codes.
5. A method for processing data using a computer, the data including bit sequences having various lengths and being generated with a reversible code, the method comprising the steps of: in the computer, transferring the data of a group when an erroneous bit is recognized by the computer in a bit sequence of the data of the group, the data being transferred so that a sequence of the bits of the data of the group become reversed, the group of data being enclosed by synchronization bit sequences; in the computer, retransferring the data of the group with the bits in reversed sequence; in the computer, comparing and decoding bit sequences up to the erroneous bit using bit sequences stored for decoding bit sequences having bits in reversed sequence.
6. The method according to claim 5 , wherein: the reversible code includes the Huffman code.
7. The method according to claim 5 , further comprising the step of: changing the group of data enclosed by synchronization bit sequences to a uniform length by padding bits.
8. The method according to claim 7 , further comprising the step of: loading known bit sequences for decoding of data that has been coded with one of reversible codes and non-reversible codes.
9. The method according to claim 8 , further comprising the step of: recognizing a beginning of the bit sequence to be decoded by the synchronization bit sequences that enclose the group of data.
10. The method according to claim 9 , further comprising the step of: storing the number of bits of the group in a counter, so that the end of the group is recognized by decrementing the counter.
11. The method according to claim 9 , further comprising the step of: storing the number of code words of the group is stored by a counter, so that the end of the group is recognized by decrementing the counter.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 7, 2000
September 16, 2003
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