A method for forming a trench type isolation film comprises filling a trench with a composite film, flattening the resultant, and annealing the flattened resultant before a gate oxide film is formed. The annealing diffuses out any contaminant existing in an area near and/or contacting the trench on a surface between a semiconductor substrate and a pad oxide film. Therefore, it is possible to prevent the portion of the gate oxide film which is near the trench from becoming thinner than other portions. Accordingly, it is possible to prevent the characteristic of the gate oxide film from deteriorating. In particular, it is possible to prevent a break down voltage from being lowered.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for forming a trench type isolation film in a semiconductor device, the method comprising: setting an active area and a field area in a semiconductor substrate; forming a mask layer above the semiconductor substrate, wherein the mask layer is configured such that it does not cover the field area and such that it does cover the active area; forming a trench in the field area of the semiconductor substrate; filling the trench in the semiconductor substrate with an insulating film; first annealing the semiconductor substrate and the filled trench; flattening an entire surface of the insulating film; second annealing the flattened resultant in an inert atmosphere to out-diffuse contaminants; and removing the mask layer after the second annealing.
2. The method of claim 1 , wherein forming a mask layer above the semiconductor substrate comprises forming a pad oxide film and forming a second insulating film above the pad oxide film.
3. The method of claim 1 , wherein flattening the entire surface of the insulating film is performed using one selected from the group consisting of chemical mechanical polishing and etching back.
4. The method of claim 1 , wherein the second annealing is performed at about 1050 degrees C., for about one hour, in an N 2 atmosphere.
5. The method of claim 1 , wherein the insulating film is formed of a composite film which comprises a first oxide film and a second oxide film.
6. The method of claim 5 , further comprising forming a contaminant shielding film, wherein the contaminant shielding film is formed between the first oxide film and the second oxide film.
7. The method of claim 6 , wherein the contaminant shielding film is a SiN film.
8. The method of claim 5 , wherein the first oxide film has a tensile force characteristic and the second oxide film has a compressive force characteristic.
9. The method of claim 5 , wherein the first oxide film is formed of undoped silicate glass (USG) and the second oxide film is formed of tetra-ethyl-orthosilicate (TEOS).
10. The method of claim 1 , wherein the second annealing is performed at a temperature not less than 1000 C.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 21, 1999
September 23, 2003
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