When a high-level bus converter receives a normal request from any one of a plurality of intermediate-level bus converters, the high-level bus converter converts the normal request into a retry response and sends the retry response to the intermediate-level bus converter, if a normal response buffer is busy. When the high-level bus converter receives an urgent request, the high-level bus converter sends a normal response in response to the urgent request to the intermediate-level bus converter. Each of a plurality of low-level bus converters issues a normal request, converts, when a retry response is received, the retry response into an urgent request, and reissues a request as the urgent request. When a plurality of urgent requests compete with each other for being processed, each of the plurality of intermediate-level bus converters arbitrates among the plurality of urgent requests, and directly transfers a winner urgent request to the high-level bus converter. Each of the plurality of intermediate-level bus converters converts at least one looser urgent request into a normal request and transfers the normal request to the high-level bus converter.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A data processing apparatus comprising at least one high-level bus converter, a plurality of intermediate-level bus converters, and a plurality of low-level bus converters which are connected with one another in hierarchy, wherein: said at least one high-level bus converter (1) converts, if a normal-response buffer is busy when a normal request is received, the received normal request into a retry response and sends the retry response to one of said plurality of intermediate-level bus converters which has sent the normal request thereto, and (2) sends, when an urgent request is received, a normal response in response to the received urgent request to one of said plurality of intermediate-level bus converters which has sent the urgent request thereto; each of said plurality of low-level bus converters (1) issues a normal request, and (2) converts, when a retry response is received, the retry response into an urgent request, and reissues a request as the urgent request; and each of said plurality of intermediate-level bus converters arbitrates, when a plurality of urgent requests compete with each other, between the plurality of urgent requests and transfers a winner urgent request to said at least one high-level bus converter, converts at least one looser urgent request into a normal request, and transfers the looser urgent request to said at least one high-level bus converter.
2. The data processing apparatus according to claim 1 , wherein: said at least one high-level bus converter (1) receives a normal request sent from one of said plurality of intermediate-level bus converters in a request buffer, converts the normal request into a retry response if the normal-response buffer is busy, and sends the retry response to the one of said plurality of intermediate-level bus converters through a retry response buffer, (2) sends, when an urgent request is received through the request buffer, a normal response in response to the urgent request to one of said plurality of intermediate-level bus converters through reserved-response entry, and (3) receives a normal response in the normal-response buffer; each of said plurality of low-level bus converters includes a request buffer, a normal-response buffer, reserved-response entry, and a retry-response buffer, (1) issues a normal request through the request buffer, (2) receives a normal response in the normal-response buffer, (3) receives a retry response in the retry-response buffer, converts the retry response into an urgent request and reissues a request as the urgent request through the request buffer; and each of said plurality of intermediate-level bus converters arbitrates, when a plurality of urgent requests are received in a request buffer so as to compete with each other, between the plurality of urgent requests, transfers a winner urgent request to said at least one high-level bus converter, converts at least one looser urgent request into a normal request, and transfers the normal request to said at least one high-level bus converter.
3. The data processing apparatus according to claim 2 , wherein each of said intermediate-level bus converters comprises: a sending-status flag register store a sending-status flag representing that an urgent request is in a middle of a process of being successfully executed, when the urgent request is transferred as an urgent request or as a normal request; a request identifier register store a valid bit representing that a request identifier and a conceding request identifier are valid; a winner identifier register store a valid bit, representing a winner identifier which is a request identifier of an urgent request determined as a winner in an urgent request arbitrator, and representing that the winner identifier is valid; and a priority pointer register storing a priority pointer for determining a winner urgent request when transferring an urgent request.
4. The data processing apparatus according to claim 3 , wherein each of said plurality of intermediate-level bus converters includes an urgent request arbitrator which determines a winner urgent request based on the priority pointer stored in the priority pointer register and the sending-status flag stored in the sending-status flag register.
5. The data processing apparatus according to claim 4 , wherein each of said plurality of intermediate-level bus converters: transfers an urgent request to said at least one high-level bus converter, when all of sending-status flags stored in the sending-status flag register are not valid and the valid bit of the winner identifier is not valid, and sets the valid bit of the winner identifier valid; transfers an urgent request to said at least one high-level bus converter, when the valid bit of the winner identifier is not valid and any one of the sending-status flags stored in the sending-status flag register is valid and when the request identifier coincides with an output of the urgent request arbitrator, and sets the valid bit of the winner identifier valid; transfers a normal request to said at least one high-level bus converter, when the valid bit of the winner identifier is not valid and any one of the sending-status flags stored in the sending-status flag register is valid and when the request identifier does not coincide with an output of the urgent request arbitrator, and sets the valid bit of the winner identifier valid; and transfers an urgent request, when the valid bit of the winner identifier is valid and when the request identifier coincides with an output of the urgent request arbitrator, and transfers a normal request when the valid bit of the winner identifier is valid and when the request identifier does not coincide with an output of the urgent request arbitrator.
6. A livelock avoidance method, as a data processing method performed by a data processing apparatus comprising a plurality of bus converters connected with each other in hierarchy, said method comprising: converting, in a bus converter having received a normal request, the normal request into a retry response, when a normal response buffer is busy, and sending the retry response to a bus converter, having issued the normal request, through reserved-response entry; reissuing a request as an urgent request for requesting an urgent service based on the retry response in the bus converter having issued the normal request; and arbitrating, when a plurality of urgent requests compete with each other in a bus converter arranged in a request path, between the plurality of urgent requests, transferring a winner urgent request to a high-level bus converter, and transferring at least one looser urgent request to the high-level bus converter as a normal request.
7. A method for processing data as performed by a data processing apparatus comprising at least one high-level bus converter, a plurality of intermediate-level bus converters and a plurality of low-level bus converters which are connected with each other in hierarchy, wherein: said high-level bus converter (1) converts, if a normal-response buffer is busy when a normal request is received, the received normal request into a retry response and sends the retry response to one of said plurality of intermediate-level bus converters which has sent the normal request thereto, and (2) sends, when an urgent request is received, a normal response in response to the received urgent request to one of said plurality of intermediate-level bus converters which has sent the urgent request thereto; each of said plurality of low-level bus converters (1) issues a normal request, and (2) converts, when a retry response is received, the retry response into an urgent request, and reissues a request as an urgent request; and each of said plurality of intermediate-level bus converters arbitrates, when a plurality of urgent requests compete with each other, between the plurality of urgent requests and transfers a winner urgent request to said high-level bus converter, converts a looser urgent request into a normal request, and transfers the looser urgent request to the high-level bus converter.
8. A data processing apparatus comprising at least one high-level bus converter, a plurality of intermediate-level converters and a plurality of low-level bus converters which are connected With each other in hierarchy, wherein: said high-level bus converter includes (1) means for converting, if a normal response buffer is busy when a normal request is received, the received normal request into a retry response and sends the retry response to one of said plurality of intermediate-level bus converters which has sent the normal request thereto, and (2) means for sending when an urgent request is received, a normal response in response to the received urgent request to one of said plurality of intermediate-level bus converters which has sent the urgent request thereto; each of said plurality of low-level bus converters includes (1) means for issuing a normal request, and (2) means for converting, when a retry response is received, the retry response into an urgent request, and reissues a request as an urgent request; and each of said plurality of intermediate-level bus converters includes means for arbitrating, when a plurality of urgent requests compete with each other, between the plurality of urgent requests and transfers a winner urgent request to said high-level bus converter, converts a looser urgent request into a normal request, and transfers the looser urgent request to the high-level bus converter.
9. A bus converter for an intermediate-level in a hierarchy in a data processing apparatus comprising at least one high-level bus converter, a plurality of intermediate-level bus converters and a plurality of low-level bus converters which are connected with each other in the hierarchy, wherein said bus converter receives an urgent request in a request buffer, arbitrates, when a plurality of urgent requests compete with each other, between the plurality of urgent requests and transfers a winner urgent request to said high-level bus converter, transfers at least one looser urgent request into a normal request, and transfers the normal request to said high-level bus converter.
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November 9, 2000
September 23, 2003
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