A semiconductor package includes a chip mounting pad having a peripheral edge. The package further includes a semiconductor chip attached to the chip mounting pad. The package further includes a plurality of leads which each have an inner end disposed adjacent the peripheral edge in spaced relation thereto and an opposing distal end. The package includes at least one isolated ring structure electrically connected to the semiconductor chip and at least one of the leads. The ring structure includes a main body portion disposed along the peripheral edge between the peripheral edge and the inner ends of the leads in spaced relation thereto, and at least one stub portion extending angularly from the main body portion along one of the leads in spaced relation thereto.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor package comprising: a chip mounting pad having a peripheral edge; a semiconductor chip attached to the chip mounting pad; a plurality of leads, each lead having an inner end disposed adjacent the peripheral edge in spaced relation thereto and an opposing distal end; at least one isolated ring structure electrically connected to the semiconductor chip and at least one of the leads and including: a main body portion disposed along the peripheral edge between the peripheral edge and the inner ends of the leads in spaced relation thereto; and at least one stub portion extending from the main body portion and along one of the leads in spaced relation thereto; a connector attached to the leads and to the stub portion for maintaining the ring structure in fixed relation to the chip mounting pad and the leads; and a package body at least partially encapsulating the chip mounting pad, the leads, the ring structure, and the connector.
2. The semiconductor package of claim 1 wherein: the main body portion includes an intermediate section; and the stub portion extends laterally from the intermediate section.
3. The semiconductor package of claim 2 wherein the stub portion extends along and between a pair of the leads.
4. The semiconductor package of claim 1 wherein: the main body portion includes opposing end sections; and the stub portion extends from one of the end sections.
5. The semiconductor package of claim 4 wherein: the at least one stub portion comprises first and second stub portions; and the first and second stub portions extend from respective ones of the end sections.
6. The semiconductor package of claim 5 wherein: the main body portion includes an intermediate section; and the at least one stub portion further comprises a third stub portion extending laterally from the intermediate section.
7. The semiconductor package of claim 1 further comprising: at least one tie bar extending from the chip mounting pad; the stub portion extending along and between the tie bar and one of the leads, with the connector being attached to the tie bar.
8. The semiconductor package of claim 1 wherein: the chip mounting pad includes a plurality of peripheral edge segments collectively defining the peripheral edge; and the at least one isolated ring structure comprises a plurality of ring structures disposed adjacent respective ones of the peripheral edge segments.
9. The semiconductor package of claim 1 wherein the at least one isolated ring structure comprises at least two ring structures electrically connected to each other.
10. The semiconductor package of claim 1 wherein: the ring structure is electrically connected to the semiconductor chip and at least one of the leads via conductive wires; and the conductive wires are at least partially encapsulated by the package body.
11. The semiconductor package of claim 1 wherein the at least one isolated ring structure comprises a plurality of ring structures disposed adjacent the peripheral edge.
12. The semiconductor package of claim 1 wherein: the at least one stub portion includes a distal section which extends in generally coplanar relation to the leads; and the main body portion and the chip mounting pad are downset relative to the distal section and the leads.
13. A method of fabricating a semiconductor package, comprising the steps of: a) providing a lead frame including: a chip mounting pad having a peripheral edge; a plurality of leads, each lead having an inner end disposed adjacent the peripheral edge in spaced relation thereto and an opposing distal end; at least one isolated ring structure including a main body portion disposed along the peripheral edge between the peripheral edge and the inner ends of the leads in spaced relation thereto, and at least one stub portion extending angularly from the main body portion and along one of the leads in spaced relation thereto; and at least one temporary connecting bar connecting the ring structure to the chip mounting pad and the leads; b) attaching a nonconductive connector to the stub portion and at least one of the leads for maintaining the ring structure in fixed relationship to the chip mounting pad and the leads; c) removing the temporary connecting bar; d) attaching a semiconductor chip to the chip mounting pad; e) electrically connecting the semiconductor chip to the ring structure; and f) electrically connecting the ring structure to at least one of the leads.
14. The method of claim 13 further comprising the step of: (g) at least partially encapsulating the chip mounting pad, the leads, the ring structure, and the connector with a package body.
15. The method of claim 13 wherein step (a) comprises forming the lead frame such that the temporary connecting bar extends between the ring structure and the chip mounting pad.
16. The method of claim 13 wherein step (a) comprises forming the lead frame such that the temporary connecting bar extends between the ring structure and at least one of the leads.
17. The method of claim 13 wherein step (b) comprises attaching adhesive tape to the stub portion and at least one of the leads.
18. The method of claim 13 wherein step (b) comprises attaching the nonconductive connector via a pick and place apparatus.
19. The method of claim 13 wherein step c) comprises removing the temporary connecting bar via a punch process.
20. The method of claim 13 wherein: step (a) comprises forming the lead frame such that at least one tie bar extends from the chip mounting pad, and the at least one stub portion extends along and between the tie bar and one of the leads; and step b) comprises attaching the nonconductive connector to the tie bar.
21. The method of claim 14 wherein: steps (e) and (f) are accomplished through the use of conductive wires; and step (g) comprises encapsulating the conductive wires with the package body.
22. The method of claim 13 wherein: step (a) comprises forming the lead frame such that the at least one isolated ring structure comprises at least two ring structures; and step f) comprises electrically connecting the at least two ring structures to each other.
23. The method of claim 13 wherein: step (a) comprises forming the lead frame such that the stub portion includes a distal section which extends in generally coplanar relation to the leads; and the method further comprises the step (g) of downsetting the main body portion and the chip mounting pad relative to the distal section and the leads.
24. A lead frame comprising: a frame defining a central opening; a chip mounting pad disposed within the central opening and attached to the frame; a plurality of leads attached to the frame and extending within the opening toward the chip mounting pad, each of the leads having an inner end disposed in spaced relation to the peripheral edge of the chip mounting pad; at least one isolated ring structure comprising: a main body portion extending between the peripheral edge and the inner ends of the leads in spaced relation thereto; and at least one stub portion extending from the main body portion along one of the leads in spaced relation thereto; and at least one temporary connecting bar connecting the ring structure to at least one of the chip mounting pad and the leads.
25. The lead frame of claim 24 wherein: the main body includes an intermediate section; and the stub portion extends laterally from the intermediate section.
26. The lead frame of claim 24 wherein the stub portion extends along and between a pair of leads.
27. The lead frame of claim 24 wherein: the main body includes opposed end sections; and the stub portion extends from one of the end sections.
28. The lead frame of claim 27 wherein: the at least one stub portion comprises first and second stub portions; and the first and second stub portions extend angularly from respective ones of the end sections.
29. The lead frame of claim 28 wherein: the main body includes an intermediate section; and the at least one stub portion further comprises a third stub portion extending laterally from the intermediate section.
30. The lead frame of claim 24 wherein the at least one isolated ring structure comprises a pair of ring structures extending between the chip mounting pad and the inner ends of the leads in spaced relation to each other.
31. The semiconductor package of claim 1 wherein the connector comprises non-conductive adhesive tape.
32. A semiconductor package comprising: a chip mounting pad having a peripheral edge; a semiconductor chip attached to the chip mounting pad; a plurality of leads, each lead having an inner end disposed adjacent the peripheral edge in spaced relation thereto and an opposing distal end; at least one isolated ring structure electrically connected to the semiconductor chip and at least one of the leads and including: a main body disposed along the peripheral edge between the peripheral edge and the inner ends of the leads in spaced relation thereto; and at least one stub portion extending from the main body portion and along one of the leads in spaced relation thereto; connector means attached to the leads and to the stub portion for maintaining the ring structure in fixed relation to the chip mounting pad and the leads; and a package body at least partially encapsulating the chip mounting pad, the leads, the ring structure, and the connector.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 9, 2002
September 30, 2003
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