A system and method are provided that reduce the amount of data held commonly in both high-ranking and low-ranking cache memories, thereby having each of those cache memories hold data more efficiently. More particularly, a computer system is provided with an HDC card 21 connected to an expansion bus 20 and an HDD unit 22 connected to the HDC card 21. The HDC card 21 is provided with a disk cache (high-ranking cache memory) and the HDD unit 22 is provided with a disk cache 54 (low-ranking cache memory). The HDC card 21 and the HDD unit 22 exchange select information for selecting a swap mode of each cache memory when the system is started up, thereby selecting different swap modes according to the exchanged select information respectively.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for controlling a plurality of cache memories in a computer system comprising a low-ranking cache memory and a high-ranking cache memory, said method comprising: operating said high-ranking cache memory in a first swap mode; operating said low-ranking cache memory in a second swap mode different from said first; exchanging select information for selecting said first and second swap modes of each cache memory when a system is started up; and each cache memory selecting a swap mode different from any other cache memory based on the exchanged select information.
2. The method for controlling a plurality of cache memories according to claim 1 , wherein one of said high-ranking and low-ranking cache memories transfers select information for selecting a swap mode of the other cache memory to the other cache memory; and said other cache memory selects its swap mode according to said select information transferred from said one cache memory.
3. The method for controlling a plurality of cache memories according to claim 2 , wherein said one cache memory selects a swap mode and identifies said selected swap mode to said other cache memory; and said other cache memory selects a swap mode different from said identified swap mode as its swap mode.
4. The method for controlling a plurality of cache memories according to claim 2 , wherein, said one cache memory transfers a plurality of swap modes that said one cache memory cannot select to said other cache memory; and said other cache memory selects one of said transferred swap modes.
5. The method for controlling a plurality of cache memories according to claim 1 , wherein said high-ranking and low-ranking cache memories are operated in different swap modes selected respectively from among an LRU (Least Recently Used) mode, an LFU (Least Frequently Used) mode, a FIFO (First-In First-Out) mode, and a mode for swapping out one of a plurality of segments holding the least amount of data.
6. The method for controlling a plurality of cache memories according to claim 1 , wherein said high-ranking cache memory is a disk cache provided for a hard disk control unit for controlling a hard disk drive unit and said low-ranking cache memory is a disk cache provided for said hard disk drive unit.
7. A method for controlling a plurality of cache memories in a computer system comprising a low-ranking cache memory and a high-ranking cache memory, said method comprising: operating said high-ranking cache memory in a first swap mode; operating said low-ranking cache memory in a second swap mode different from said first; exchanging select information for selecting said first and second swap modes of each cache memory when a system is started up; each cache memory selecting a swap mode different from any other cache memory based on the exchanged select information; one of said high-ranking and low-ranking cache memories transferring a plurality of swap modes for selection to an other cache memory; said other cache memory selecting one of said transferred swap modes; notifying said one cache memory to select said selected swap mode; said other cache memory selecting a swap mode different from said responded swap mode as its swap mode; and said one cache memory selecting said notified swap mode as its swap mode.
8. A computer system, comprising: a low-ranking cache memory; a high-ranking cache memory connected to said low-ranking cache memory; and an information exchanger between said high-ranking and low-ranking cache memories through which select information for selecting a swap mode is exchanged wherein each cache memory selects different swap modes respectively according to said exchanged select information.
9. The computer system according to claim 2 , further comprising: a transferring device in one of said high-ranking andlow-ranking cache memories for transferring to another of said cache memories select information for selecting a swap mode of said other cache memory; and a selecting device in said other cache memory for selecting its swap mode according to said select information received from said one cache memory.
10. The computer system according to claim 9 , further comprising: a mode selecting device in said one cache memory for selecting its swap mode, wherein said transferring device transfers a swap mode selected by said mode selecting device to the other cache memory, and said selecting device of said other cache memory selects a swap mode different from said swap mode received from said one cache memory as a swap mode of said other cache memory.
11. The computer system according to claim 9 , wherein said transferring device of said one cache memory transfers a plurality of swap modes that said one cache memory cannot select, to the other cache memory; and said selecting device of said other cache memory selects one of the plurality of said swap modes received from said one cache memory as its swap mode.
12. The computer system according to claim 8 , wherein said high-ranking cache memory and said low-ranking cache memory are operated in different swap modes selected from LRU (Least Recently Used) mode, LFU (Least Frequently Used) mode, FIFO ( First-In First-Out) mode, and a mode for swapping out a segment holding the least amount of data among a plurality of segments.
13. The computer system according to claim 8 , wherein said high-ranking cache memory is a disk cache provided for a hard disk control unit for controlling a hard disk unit; and said low-ranking cache memory is a disk cache provided for said hard disk drive unit.
14. The computer system of claim 8 , further comprising: a hard disk drive unit provided with a cache memory for holding a portion of data stored in a magnetic disk wherein said low-ranking cache memory is said hard disk drive cache memory; and a main memory for holding a portion of data stored in a hard disk drive unit and sending/receiving data to/from said hard disk drive unit according to an instruction issued from a central processing unit wherein said high-ranking cache memory is said main memory.
15. A computer system, comprising: a low-ranking cache memory; a high-ranking cache memory connected to said low-ranking cache memory; and an information exchanger between said high-ranking and low-ranking cache memories through which select information for selecting a swap mode is exchanged wherein each cache memory selects different swap modes respectively according to said exchanged select information; a candidate mode transferring device in one of said high-ranking and low-ranking cache memories for transferring a plurality of swap modes that said one cache memory is capable of selecting to the other cache memory; a mode selecting device in said one cache memory for selecting said swap mode received from said other cache memory as said one cache memory swap mode; a partner's mode selecting device in said other cache memory for selecting a swap mode that said one cache memory should select, from among a plurality of said swap modes received from said one cache memory; a partner's mode transferring device in said other cache memory for transferring a swap mode selected by said other cache memory for said one cache memory to said one cache memory; and a self-mode selecting device in said other cache memory for selecting a swap mode different from said swap mode selected by said partner's mode selecting device as a swap mode of said other cache memory.
16. A hard disk control unit, comprising: a first connection terminal connected to a connection terminal of a peripheral device provided for a computer system; a second connection terminal connected to a hard disk drive unit having a low-ranking cache memory for storing part of data stored in a storage media; and a high-ranking cache memory for holding a portion of data stored in said hard disk drive unit connected to said second connection terminal; a controller for controlling said hard disk unit connected to said second connection terminal; an information exchanger between said high-ranking and said low-ranking cache memories for selecting a swap mode of each cache memory so as to be operated in different swap modes when said computer system connected to said first connection terminal is started up; and a swap mode selector for selecting a swap mode of said high-ranking cache memory according to said exchanged select information.
17. A hard disk control unit, comprising: a first connection terminal connected to a connection terminal of peripheral device provided for a computer system provided with a host system having functions of a high-ranking cache memory; a second connection terminal connected to a hard disk drive unit; and a low-ranking cache memory for holding a portion of data stored in said hard disk drive unit connected to said second connection terminal; a controller for controlling said hard disk drive unit connected to said second connection terminal; an information exchanger between said high-ranking cache memory and said low-ranking cache memory for selecting swap modes as so to be operated in different swap modes when said computer system connected to said first connection terminal is started up; and a swap mode selector for selecting a swap mode of said low-ranking cache memory according to said exchanged select information.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 13, 2000
September 30, 2003
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