Leakage detection in a programming algorithm for a flash memory device. According to one embodiment of the present invention a method includes programming a first flash cell in an array of flash cells in a flash memory device, sequentially selecting flash cells connected to the first flash cell, testing each selected flash cell to determine if the selected flash cell is leaky, and applying a refresh pulse to the selected flash cell if the selected flash cell is leaky. According to another embodiment of the present invention a flash memory device includes an array of flash cells, a program circuit to apply a programming pulse to program a first flash cell in the array, and a control circuit including elements to sequentially select flash cells connected to the first flash cell, test each selected flash cell to determine if the selected flash cell is leaky, and cause the program circuit to apply a refresh pulse to the selected flash cell if the selected flash cell is leaky.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A flash memory device comprising: an array of flash cells; a program circuit to apply a programming pulse to program a first flash cell in the array; and a control circuit comprising elements to: sequentially select flash cells connected to the first flash cell; test each selected flash cell to determine if the selected flash cell is leaky; and cause the program circuit to apply a refresh pulse to the selected flash cell if the selected flash cell is leaky.
2. The flash memory device of claim 1 , wherein the flash memory device is an integrated circuit embedded with another integrated circuit in an integrated circuit chip.
3. The flash memory device of claim 1 , wherein the control circuit further comprises elements to: test the selected flash cell after each refresh pulse is applied to determine if the selected flash cell is leaky; and cause the program circuit to apply a refresh pulse to the selected flash cell if the selected flash cell is leaky.
4. The flash memory device of claim 3 , wherein the control circuit further comprises elements to: reset a counter when the selected flash cell is selected; increment the counter each time a refresh pulse is applied to the selected flash cell; and terminate the testing of the selected flash cell with an error if the counter exceeds a predetermined value.
5. The flash memory device of claim 1 , wherein the elements to sequentially select flash cells comprise elements to sequentially select flash cells connected to a bit line or a word line that is connected to the first flash cell.
6. A flash memory device comprising: an array of flash cells; a program circuit to apply a programming pulse to program a first flash cell in the array; and a control circuit comprising elements to: select a second flash cell connected to the first flash cell; test the second flash cell to determine if the second flash cell is leaky; and cause the program circuit to apply a refresh pulse to the second flash cell if the second flash cell is leaky.
7. The flash memory device of claim 6 , wherein the flash memory device is an integrated circuit embedded with another integrated circuit in an integrated circuit chip.
8. The flash memory device of claim 6 , wherein the control circuit further comprises elements to: read the second flash cell to generate a read signal; compare the read signal with a first reference signal to indicate data stored in the second flash cell; and compare the read signal with a second reference signal to indicate if the second flash cell is leaky.
9. The flash memory device of claim 6 , wherein the control circuit further comprises elements to: sequentially select flash cells connected to a bit line that is connected to the first flash cell; test each selected flash cell to determine if the selected flash cell is leaky; and apply a refresh pulse to the selected flash cell if the selected flash cell is leaky.
10. The flash memory device of claim 6 , wherein the control circuit further comprises elements to: test the second flash cell repeatedly to determine if the second flash cell is leaky; apply a refresh pulse to the second flash cell each time it is determined that the second flash cell is leaky; and terminate the testing of the second flash cell when it is determined that the second flash cell is repaired.
11. The flash memory device of claim 10 , wherein the control circuit further comprises elements to: increment a counter each time the refresh pulse is applied to the second flash cell; and terminate the testing of the second flash cell with an error if the counter exceeds a predetermined value.
12. A flash memory device comprising: an array of flash cells; and a control circuit programmed to: apply a programming pulse to a first flash cell in the array; sequentially select flash cells connected to the first flash cell; test each selected flash cell to determine if the selected flash cell is leaky; and apply a refresh pulse to the selected flash cell if the selected flash cell is leaky.
13. The flash memory device of claim 12 , wherein the flash memory device is an integrated circuit embedded with another integrated circuit in an integrated circuit chip.
14. The flash memory device of claim 12 , wherein the control circuit is further programmed to: test the selected flash cell after a refresh pulse is applied to determine if the selected flash cell is leaky; and apply a refresh pulse to the selected flash cell if the selected flash cell is leaky.
15. The flash memory device of claim 14 , wherein the control circuit is further programmed to: reset a counter when the selected flash cell is selected; increment the counter each time a refresh pulse is applied to the selected flash cell; and terminate the testing of the selected flash cell with an error if the counter exceeds a predetermined value.
16. The flash memory device of claim 12 wherein the control circuit is further programmed to sequentially select flash cells connected to a bit line or a word line that is connected to the first flash cell.
17. A flash memory device comprising: an array of flash cells; and a control circuit programmed to: select a flash cell in the array of flash cells; test the selected flash cell to determine if the selected flash cell is leaky; and apply a refresh pulse to the selected flash cell if the selected flash cell is leaky.
18. The flash memory device of claim 17 , wherein the flash memory device is an integrated circuit embedded with another integrated circuit in an integrated circuit chip.
19. The flash memory device of claim 17 , wherein the control circuit further comprises elements to: test the selected flash cell after each refresh pulse is applied to determine if the selected flash cell is leaky; and cause the program circuit to apply a refresh pulse to the selected flash cell if the selected flash cell is leaky.
20. A flash memory device comprising: an array of flash cells; and a control circuit including: a first comparison circuit that checks if a signal from a selected flash cell is above a first value; a second comparison circuit that checks if the signal from the selected flash cell is below a second value; and a refresh circuit the applies a refresh pulse to the selected flash cell if the signal from the selected flash cell is between the first value and the second value.
21. The flash memory device of claim 20 , wherein the signal from the selected flash cell includes a current in the flash cell.
22. The flash memory device of claim 21 , wherein the first value is approximately 30 microamps and the second value is approximately 20 microamps.
23. The flash memory device of claim 20 , wherein the flash memory device is an integrated circuit embedded with another integrated circuit in an integrated circuit chip.
24. The flash memory device of claim 20 , wherein the control circuit further comprises elements to: test the selected flash cell after the refresh pulse is applied to determine if the signal from the selected flash cell is between the first value and the second value; and cause the program circuit to apply a second refresh pulse to the selected flash cell if the signal from the selected flash cell is between the first value and the second value.
25. A flash memory device comprising: an array of flash cells; and a control circuit programmed to: select a flash cell in the array of flash cells; test the selected flash cell to determine if the selected flash cell is leaky; apply a first refresh pulse to the selected flash cell if the selected flash cell is leaky; test the selected flash cell after the first refresh pulse is applied to determine if the selected flash cell is leaky; and apply a second refresh pulse to the selected flash cell if the selected flash cell is leaky.
26. The flash memory device of claim 25 , wherein the flash memory device is an integrated circuit embedded with another integrated circuit in an integrated circuit chip.
27. A flash memory device comprising: an array of flash cells; and a control circuit programmed to: select a flash cell in the array of flash cells; test the selected flash cell to determine if the selected flash cell is leaky; and apply a first refresh pulse to the selected flash cell if the selected flash cell is leaky; and retest the selected flash cell and apply subsequent refresh pulses to the selected flash cell if the selected flash cell is leaky, wherein a counter is incremented each time a refresh pulse is applied to the selected flash cell.
28. The flash memory device of claim 27 , wherein testing of the selected flash cell is terminated with an error if the counter exceeds a predetermined value.
29. A flash memory device comprising: an array of flash cells; a programming circuit to apply a programming pulse to a first flash cell in the array; means for sequentially selecting flash cells connected to the first flash cell; means for testing each selected flash cell to determine if the selected flash cell is leaky; and means for applying a refresh pulse to the selected flash cell if the selected flash cell is leaky.
30. The flash memory device of claim 27 , wherein the means for testing each selected flash cell includes: a first comparison circuit that checks if a signal from a selected flash cell is above a first value; and a second comparison circuit that checks if the signal from the selected flash cell is below a second value.
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August 29, 2002
November 18, 2003
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