A hub based computer system having a central hub that communicates with a plurality of satellite devices over respective link buses. Each link bus is substantially the same and adheres to a predefined link bus protocol. The link bus protocol establishes a method in which data receiving circuitry of a target device can be put into a known state during a final stage of a source strobe event such as e.g., a data transfer. Once in the known state, the source strobes are stopped on the link bus. The target device uses internal logic clocked by a system clock rather than the source strobe to continuously sample the state of the receiving circuitry to see if the state has deviated from the known state. A change detect circuit determines if the receiving circuitry has deviated from the known state and if so, detects a new source strobe event. The change detect circuit detects the new event in the less stringent clock domain, which allows greater control of the skew and asymmetry of the source strobe. This allows the system to achieve substantially higher data transfer rates than conventional source strobe systems.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of detecting a source strobe event in a processor based system, the system comprising a first device coupled to a second device by a link bus, the link bus comprising at least one source strobe signal line associated with a first clock domain, said method comprising the steps of: inputting at one of the first and second device information associated with the source strobe event from the link bus, the information being input into first circuitry associated with the first clock domain; sampling the input information from the first circuitry into second circuitry associated with a second clock domain; determining from the sampled information whether the link bus is in a known state; and processing the source strobe event if it is determined that the link bus is not in the known state.
2. The method of claim 1 , wherein the known state is a link bus idle state.
3. The method of claim 1 , wherein the information associated with the source strobe event is a command packet transmitted over the link bus from the other one of the first and second device.
4. The method of claim 1 , further comprising the step of ignoring the information if it is determined that the link bus is in the known state.
5. The method of claim 4 , wherein if it is determined that the link bus is in the known state, said method further comprises: repeating said inputting step to said determining step until it is determined that the link bus is not in the known state.
6. The method of claim 1 , wherein said determining step comprises: determining whether the sampled information should be presently checked; and if it is determined that the information should be presently checked, comparing the sampled information to information indicative of the known state.
7. The method of claim 6 , wherein said step of determining whether the sampled information should be presently checked comprises: checking a characteristic of a prior source strobe event; and determining from the checked characteristic whether it is possible for a new source strobe event to occur at present.
8. The method of claim 7 , wherein the characteristic is a packet count of the prior source strobe event.
9. The method of claim 1 , wherein said inputting step comprises: detecting a source strobe propagating in the at least one source strobe signal line; and inputting the input information from a command/address/data portion of the link bus.
10. The method of claim 9 , wherein said sampling step comprises: generating simulated source strobes based on the detected source strobe; latching the input information within the first circuitry using the simulated source strobes; and clocking the latched information into the second circuitry based on a clock signal generated in the second clock domain.
11. The method of claim 1 , wherein the other one of the first and second device terminates the issuance of source strobes on the source strobe line at a completion of the source strobe event.
12. The method of claim 11 , wherein the other one of the first and second device continues the issuance of source strobes on the source strobe line at a beginning of a new source strobe event.
13. A method of detecting a source strobe event in a processor based system, the system comprising a hub device coupled to a processor by a processor bus and coupled to a memory device by a memory bus, the hub device being connected to a satellite device by a link bus, the link bus comprising at least one source strobe signal line associated with a first clock domain, said method comprising the steps of: inputting at one of the hub device and the satellite device information associated with the source strobe event from the link bus, the information being input into first circuitry associated with the first clock domain; sampling the input information from the first circuitry into second circuitry associated with a second clock domain; determining from the sampled information whether the second circuitry is in a known state; and processing the source strobe event if it is determined that the second circuitry is not in the known state.
14. The method of claim 13 , wherein the known state is an idle state.
15. The method of claim 13 , wherein the information associated with the source strobe event is a command packet transmitted over the link bus from the other one of the hub device and satellite device.
16. The method of claim 13 , further comprising the step of ignoring the information if it is determined that the second circuitry is in the known state.
17. The method of claim 16 , wherein if it is determined that the second circuitry is in the known state, said method further comprises: repeating said inputting step to said determining step until it is determined that the second circuitry is not in the known state.
18. The method of claim 13 , wherein said determining step comprises: determining whether the sampled information should be presently checked; and if it is determined that the information should be presently checked, sending a signal to change detect circuitry such that the change detect circuitry compares the sampled information to information indicative of the known state.
19. The method of claim 18 , wherein said step of determining whether the sampled information should be presently checked comprises: checking a characteristic of a prior source strobe event; and determining from the checked characteristic whether it is possible for a new source strobe event to occur at present.
20. The method of claim 19 , wherein the characteristic is a packet count of the prior source strobe event.
21. The method of claim 13 , wherein said inputting step comprises: detecting a source strobe propagating in the at least one source strobe signal line; and inputting the input information from a command/address/data portion of the link bus.
22. The method of claim 21 , wherein said sampling step comprises: generating simulated source strobes based on the detected source strobe; latching the input information within the first circuitry using the simulated source strobes; and clocking the latched information into the second circuitry based on a clock signal generated in the second clock domain.
23. The method of claim 13 , wherein the other one of the hub device and the satellite device terminates the issuance of source strobes on the source strobe line at a completion of the source strobe event.
24. The method of claim 23 , wherein the other one of the hub device and the satellite device continues the issuance of source strobes on the source strobe line at a beginning of a new source strobe event.
25. A receiving circuit for detecting and receiving a source strobe event from a source strobed bus, said circuit comprising: a first data circuit for inputting information associated with the source strobe event from the bus, said first data circuit having a first output and being clocked by a source strobe signal associated with the bus; a second data circuit connected to said first output, said second data circuit having a second output and being clocked by a second clock signal associated with a clock of said receiving circuit, said second data circuit continuously sampling said first output and outputting said second output responsive to said second clock signal; and a change detect circuit connected to receive said second output, said change detect circuit determining whether said second data circuit is in a known state and processing the source strobe event if it is determines that said second data circuit is not in the known state.
26. The receiving circuit of claim 25 , wherein the known state is a bus idle state.
27. The receiving circuit of claim 25 , wherein the information associated with the source strobe event is a command packet transmitted over the bus from a master of the bus.
28. The receiving circuit of claim 25 , wherein said change detect circuit ignores the information if it is determined that the second circuit is in the known state.
29. The receiving circuit of claim 25 , wherein said change detect circuit determines whether said second data circuit is in a known state by determining whether said second output should be presently checked and comparing information from said second output to information indicative of the known state when it determines that said second output should be checked.
30. The receiving circuit of claim 29 , wherein said change detect circuit determines whether said second output should be checked by checking a characteristic of a prior source strobe event and determining from the checked characteristic whether it is possible for a new source strobe event to occur at present.
31. The receiving circuit of claim 30 , wherein the characteristic is a packet count of the prior source strobe event.
32. The receiving circuit of claim 25 , wherein said first data circuit inputs the information by detecting the source strobe signal and inputting the information from a command/address/data portion of the source strobed bus.
33. The receiving circuit of claim 32 , wherein said first data circuit generates simulated source strobes based on the detected source strobe and latches the input information using the simulated source strobes.
34. A receiving circuit for detecting and receiving a source strobe event from a source strobed bus, said circuit comprising: a source strobe macro connected to the source strobe bus, said source strobe macro receiving source strobes from the bus, generating a plurality of additional strobes based on the received strobes and outputting said additional strobes; a plurality of data macros connected to the source strobe bus and to the additional strobes, each of said plurality of data macros inputting information associated with the source strobe event from the bus and in response to said additional strobes, sampling the information into a clock domain associated with a core logic clock of said receiving circuit and outputting clock domain information; and a change detect circuit connected to receive said clock domain information and a control signal, said change detect circuit in response to said control signal determines whether the bus is a known state based on said clock domain information and processes the source strobe event when the bus is not in the known state.
35. The receiving circuit of claim 34 , wherein said control signal is generated by the core logic when a new source strobe event is expected.
36. The receiving circuit of claim 34 , wherein said control signal is generated by the core logic when a characteristic of a prior source strobe event indicates that a new source strobe event may occur.
37. The receiving circuit of claim 36 , wherein said characteristic is a packet count of the prior source strobe event.
38. The receiving circuit of claim 34 , wherein the source strobe event is a data transfer on the source strobe bus.
39. The receiving circuit of claim 34 , wherein the known state is a bus idle state.
40. The receiving circuit of claim 34 , wherein the information associated with the source strobe event is a command packet transmitted over the bus from a master of the bus.
41. The receiving circuit of claim 34 , wherein the source strobe bus comprises a second source strobe and said receiving circuit further comprises a second strobe macro connected to receive the second source strobe, and to generate and output a plurality of second additional strobes based on the received additional strobe.
42. The receiving circuit of claim 34 , wherein each data macro comprises: a strobe toggle circuit connected to input said additional strobes, said strobe toggle circuit generating and outputting toggle strobes to simulate the additional strobes even if said additional strobes are not received; a first data circuit for inputting the information associated with the source strobe event from the source strobe bus, said first data circuit having a first output and being clocked by the generated toggle strobes; and a second data circuit connected to said first output, said second data circuit having a second output connected to said change detect circuit and being clocked by a clock signal associated with the core logic clock, said second data circuit continuously sampling said first output and outputting said second output responsive to said clock signal.
43. The receiving circuit of claim 34 , wherein said change detect circuit comprises: a plurality of latches, each latch receiving and latching a respective portion of said clock domain information in response to a clock signal associated with the core logic clock, each latches outputting respective latched clock domain information; a plurality of comparison circuits, each comparison circuit inputting a respective portion of said clock domain information and said latched clock domain information and determining whether the portions match, each comparison circuit outputting a respective comparison output signal when the portions match; and an AND gate connected to receive the comparison output signals and the control signal, said AND gate outputting a new source strobe event signal if the comparison output signals and the control signal indicate that a new source strobe event has occurred.
44. A processor based system comprising: a processor; a link hub coupled to said processor by a processor bus; a satellite device coupled to said link hub by a link bus, said link bus being a source strobed bus, at least one of said satellite device and said link hub including a receiving circuit for detecting and receiving a source strobe event from said link bus, said receiving circuit comprising: a first data circuit for inputting information associated with the source strobe event from said bus, said first data circuit having a first output and being clocked by a source strobe signal associated with said bus; a second data circuit connected to said first output, said second data circuit having a second output and being clocked by a second clock signal associated with a clock of said receiving circuit, said second data circuit continuously sampling said first output and outputting said second output responsive to said second clock signal; and a change detect circuit connected to receive said second output, said change detect circuit determining whether said second data circuit is in a known state and processing the source strobe event if it is determines that said second data circuit is not in the known state.
45. The system of claim 44 , wherein the known state is a bus idle state.
46. The system of claim 44 , wherein the information associated with the source strobe event is a command packet transmitted over the bus from a master of the bus.
47. The system of claim 44 , wherein said change detect circuit ignores the information if it is determined that the second circuit is in the known state.
48. The system of claim 44 , wherein said change detect circuit determines whether said second data circuit is in a known state by determining whether said second output should be presently checked and comparing information from said second output to information indicative of the known state when it determines that said second output should be checked.
49. The system of claim 48 , wherein said change detect circuit determines whether said second output should be checked by checking a characteristic of a prior source strobe event and determining from the checked characteristic whether it is possible for a new source strobe event to occur at present.
50. The system of claim 49 , wherein the characteristic is a packet count of the prior source strobe event.
51. The system of claim 44 , wherein the other one of said link hub and said satellite device includes a receiving circuit.
52. A processor based system comprising: a processor; a link hub coupled to said processor by a processor bus; a satellite device coupled to said link hub by a link bus, said link bus being a source strobed bus, at least one of said satellite device and said link hub including a receiving circuit for detecting and receiving a source strobe event from said link bus, said receiving circuit comprising: a source strobe macro connected to said link bus, said source strobe macro receiving source strobes from said bus, generating a plurality of additional strobes based on the received strobes and outputting said additional strobes; a plurality of data macros connected to said link bus and to the additional strobes, each of said plurality of data macros inputting information associated with the source strobe event from said bus and in response to said additional strobes, sampling the information into a clock domain associated with a core logic clock of said receiving circuit and outputting clock domain information; and a change detect circuit connected to receive said clock domain information and a control signal, said change detect circuit in response to said control signal determines whether said bus is a known state based on said clock domain information and processes the source strobe event when said bus is not in the known state.
53. The system of claim 52 , wherein said control signal is generated by the core logic when a new source strobe event is expected.
54. The system of claim 52 , wherein said control signal is generated by the core logic when a characteristic of a prior source strobe event indicates that a new source strobe event may occur.
55. The system of claim 54 , wherein said characteristic is a packet count of the prior source strobe event.
56. The system of claim 52 , wherein the source strobe event is a data transfer on the source strobe bus.
57. The system of claim 52 , wherein the known state is a bus idle state.
58. The system of claim 52 , wherein the information associated with the source strobe event is a command packet transmitted over said bus from a master of said bus.
59. The system of claim 52 , wherein said link bus comprises a second source strobe and said receiving circuit further comprises a second strobe macro connected to receive the second source strobe, and to generate and output a plurality of second additional strobes based on the received additional strobe.
60. The system of claim 52 , wherein each data macro comprises: a strobe toggle circuit connected to input said additional strobes, said strobe toggle circuit generating and outputting toggle strobes to simulate the additional strobes even if said additional strobes are not received; a first data circuit for inputting the information associated with the source strobe event from the source strobe bus, said first data circuit having a first output and being clocked by the generated toggle strobes; and a second data circuit connected to said first output, said second data circuit having a second output connected to said change detect circuit and being clocked by a clock signal associated with the core logic clock, said second data circuit continuously sampling said first output and outputting said second output responsive to said clock signal.
61. The system of claim 52 , wherein said change detect circuit comprises: a plurality of latches, each latch receiving and latching a respective portion of said clock domain information in response to a clock signal associated with the core logic clock, each latches outputting respective latched clock domain information; a plurality of comparison circuits, each comparison circuit inputting a respective portion of said clock domain information and said latched clock domain information and determining whether the portions match, each comparison circuit outputting a respective comparison output signal when the portions match; and an AND gate connected to receive the comparison output signals and the control signal, said AND gate outputting a new source strobe event signal if the comparison output signals and the control signal indicate that a new source strobe event has occurred.
62. The system of claim 52 , wherein the other one of said link hub and said satellite device includes a receiving circuit.
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December 7, 2000
November 18, 2003
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