Patentable/Patents/US-6654855
US-6654855

Method and apparatus for improving the efficiency of cache memories using chained metrics

PublishedNovember 25, 2003
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A time-weighted metric is associated with each line of data that is being held in a data cache. The value of the metric is recomputed as the lines are accessed and the metric value is used to group cache lines for paging purposes. The metrics are computed and stored and the stored metrics are maintained by linking the storage locations together in several linked lists that allow the metrics to be easily manipulated for updating purposes and for determining which metrics represent the most active cache lines. In particular, indices are maintained which identify linked lists of metrics with similar values. At regular predetermined time intervals, these indices are then used to assemble an ordered linked list of metrics corresponding to cache lines with similar metric values. This ordered list can be traversed in order to select cache lines for removal.

Patent Claims
30 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A method for use in a computer system in which cache lines in a cache memory are transferred in a multi-line page between the cache memory and an underlying storage, the method determining which cache lines to group in a page for removal from the cache memory in order to make room for new data and comprising: (a) associating a metric having a value with each cache line in a page when the page is brought into the cache memory; (b) changing a value of a metric each time the associated cache line is accessed by the computer system; (c) repeatedly arranging metrics in a chain in which metric values are ordered first by a time duration during which associated cache lines were last accessed and then by the value of the metric; and (d) using sequential metric values from the chain to select cache lines in order to build a page for removal from the cache memory.

2

2. The method of claim 1 wherein the chain comprises a connected set of metric sub-chains, the sub-chains being linked in order of a time duration in which cache lines associated with metrics in each sub-chain were last accessed and metrics within each sub-chain being ordered in accordance with their associated metric values.

3

3. The method of claim 2 wherein each of the sub-chains comprises a linked list of metrics having a same metric value.

4

4. The method of claim 2 further comprising (e) defining sequential time intervals and wherein step (c) comprises assembling a set of sub-chains during each time interval and, at the end of the time interval, linking the assembled set of sub-chains together.

5

5. The method of claim 4 wherein the chain has a length and wherein each time interval ends when a combined length of the sub-chains assembled during that time interval substantially equals the chain length.

6

6. The method of claim 1 wherein step (a) comprises associating a metric having a value equal to a number of times the associated cache line has been accessed since being brought into the cache memory.

7

7. The method of claim 6 wherein step (b) comprises incrementing the value of the metric each time the associated cache line is accessed by the computer system.

8

8. The method of claim 1 wherein the chain comprises a doubly linked list.

9

9. The method of claim 1 wherein each cache line has an address in the cache memory and wherein step (a) comprises storing the metrics in a data structure in which a metric associated with a cache line is accessed in the data structure using the address of the cache line in the cache memory.

10

10. The method of claim 9 wherein each metric is stored in an entry in the data structure and the chain is formed by linking entries in the data structure using the addresses.

11

11. The method of claim 10 wherein the chain has a head and a tail and wherein the method further comprises (f) storing an entry address of the head and an entry address of the tail in another data structure.

12

12. Apparatus for use in a computer system in which cache lines in a cache memory are transferred in a multi-line page between the cache memory and an underlying storage, the apparatus determining which cache lines to group in a page for removal from the cache memory in order to make room for new data and comprising: a structure that associates a metric having a value with each cache line in a page when the page is brought into the cache memory; an access-response mechanism that changes a value of a metric each time an associated cache line is accessed by the computer system; a merge mechanism that repeatedly arranges metrics in a chain in which metric values are ordered first by a time duration during which associated cache lines were last accessed and then by the value of the metric; and an extraction mechanism that uses sequential metric values from the chain to select cache lines in order to build a page for removal from the cache memory.

13

13. The apparatus of claim 12 wherein the chain comprises a connected set of sub-chains, the sub-chains being linked in order of a time duration in which associated cache lines were last accessed and metrics within each sub-chain being ordered in accordance with their associated metric values.

14

14. The apparatus of claim 13 wherein each of the sub-chains comprises a linked list of metrics having a same metric value.

15

15. The apparatus of claim 13 further comprising a timing mechanism that defines sequential time intervals and wherein the merge mechanism comprises an M-list for assembling a set of sub-chains during each time interval and a mechanism, operable at the end of the time interval, that links the assembled set of sub-chains together.

16

16. The apparatus of claim 15 wherein the chain has a length and wherein each time interval ends when a combined length of the sub-chains assembled during that time interval substantially equals the chain length.

17

17. The apparatus of claim 12 wherein the structure associates a metric having a value equal to a number of times an associated cache line has been accessed since being brought into the cache memory.

18

18. The apparatus of claim 17 wherein the access-response mechanism comprises a counter that increments a value of a metric each time an associated cache line is accessed by the computer system.

19

19. The apparatus of claim 12 wherein the chain comprises a doubly linked list.

20

20. The apparatus of claim 12 wherein each cache line has an address in the cache memory and wherein the structure comprises a data structure in which metrics are stored and in which a metric associated with a cache line is accessed in the data structure using an address of the cache line in the cache memory.

21

21. The apparatus of claim 20 wherein each metric is stored in an entry in the data structure and the chain is formed by linking entries in the data structure using the addresses.

22

22. The apparatus of claim 21 wherein the chain has a head and a tail and the apparatus further comprises another data structure that stores an entry address of the head and an entry address of the tail.

23

23. A computer program product for use in a computer system in which cache lines in a cache memory are transferred in a multi-line page between the cache memory and an underlying storage, a method determining which cache lines to group in a page for removal from the cache memory in order to make room for new data, the computer program product comprising a computer usable medium having computer readable program code thereon, including: program code that associates a metric having a value with each cache line in a page when the page is brought into the cache memory; program code that changes a value of a metric each time the associated cache line is accessed by the computer system; program code that repeatedly arranges metrics in a chain in which metric values are ordered first by a time duration during which associated cache lines were last accessed and then by the value of the metric; and program code that uses sequential metric values from the chain to select cache lines in order to build a page for removal from the cache memory.

24

24. The computer program product of claim 23 wherein the chain comprises a connected set of metric sub-chains, the sub-chains being linked in order of a time duration in which cache lines associated with metrics in each sub-chain were last accessed and metrics within each sub-chain being ordered in accordance with their associated metric values.

25

25. The computer program product of claim 24 wherein each of the sub-chains comprises a linked list of metrics having a same metric value.

26

26. The computer program product of claim 24 further comprising program code that defines sequential time intervals and wherein the program code that arranges metrics in a chain comprises program code that assembles a set of sub-chains during each time interval and, at the end of the time interval, links the assembled set of sub-chains together.

27

27. The computer program product of claim 26 wherein the chain has a length and wherein each time interval ends when a combined length of the sub-chains assembled during that time interval substantially equals the chain length.

28

28. The computer program product of claim 23 wherein the program code that associates a metric with each cache line comprises program code that associates a metric having a value equal to a number of times the associated cache line has been accessed since being brought into the cache memory.

29

29. The computer program product of claim 28 wherein the program code that recomputes a value of a metric each time the associated cache line is accessed by the computer system comprises program code that increments the value of the metric each time the associated cache line is accessed by the computer system.

30

30. A computer data signal embodied in a carrier wave for use in a computer system in which cache lines in a cache memory are transferred in a multi-line page between the cache memory and an underlying storage, a method determining which cache lines to group in a page for removal from the cache memory in order to make room for new data, the computer data signal comprising: program code that associates a metric having a value with each cache line in a page when the page is brought into the cache memory; program code that changes a value of a metric each time the associated cache line is accessed by the computer system; program code that repeatedly arranges metrics in a chain in which metric values are ordered first by a time duration during which associated cache lines were last accessed and then by the value of the metric; and program code that uses sequential metric values from the chain to select cache lines in order to build a page for removal from the cache memory.

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Patent Metadata

Filing Date

March 12, 2001

Publication Date

November 25, 2003

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