A semiconductor device including storage nodes of a capacitor and a method for manufacturing the same are provided. Bit lines are formed on a semiconductor substrate, and protection layers are formed to cover and protect the bit lines. Conductive contact pads are formed between the bit lines and are level with the top surfaces of the protection layers. A node supporting layer is formed to cover the conductive contact pads and the protection layers. An etching stopper is formed on the node supporting layer. The mold layer, the etching stopper, and the node supporting layer are patterned, thereby forming opening holes exposing the conductive pads. Storage nodes are formed in the opening holes and have the shape of the profile of the opening holes. The mold layer exposed by the storage nodes is removed, thereby exposing the outer wall of each of the storage nodes positioned above the etching stopper.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for manufacturing a semiconductor device comprising: forming bit lines and protection layers for covering each of the bit lines on a semiconductor substrate; forming conductive contact pads between the bit lines to a height level with the top surfaces of the protection layers; forming a node supporting layer covering the conductive contact pads and the protection layers; forming an etching stopper on the node supporting layer; forming a mold layer on the etching stopper; forming opening holes to expose the conductive contact pads by patterning the mold layer, the etching stopper, and the node supporting layer; forming storage nodes in the opening holes, the storage nodes having the shape of the profile of the opening holes; and exposing the outer walls of the storage nodes positioned above the etching stopper by removing the exposed mold layer.
2. The method of claim 1 , wherein the step of forming the conductive contact pads comprises the steps of: forming an interlayer insulating layer to fill a gap between the bit lines; patterning the interlayer insulating layer to expose the top surface and side walls of each of the protection layers covering the bit lines; forming a conductive layer to be electrically connected to the semiconductor substrate by filling a gap between the side walls of the protection layers with a conductive material; and sequentially planarizing the conductive layer and the interlayer insulating layer to expose the top surface of each of the protection layers.
3. The method of claim 2 , wherein the interlayer insulating layer covers two facing lateral sides of adjacent conductive contact pads, and each of the protection layers covers the other facing lateral sides of adjacent conductive contact pads.
4. The method of claim 2 , wherein the step of sequentially planarizing the conductive layer and the interlayer insulating layer is performed by at least one of etch back and chemical mechanical polishing.
5. The method of claim 1 , wherein the node supporting layer is formed of silicon oxide.
6. The method of claim 1 , wherein the thickness of the node supporting layer accounts for about 20-40% of the thickness of the mold layer.
7. The method of claim 1 , wherein the step of removing the mold layer stops at the surface of the etching stopper.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 19, 2002
December 2, 2003
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