A data reception unit for receiving a plurality of data streams over a data channel. The data streams are received as amounts of data, each amount of data comprising a data portion including data from a data stream and an identity portion identifying that data stream. The data reception unit comprises a data stream memory comprising a plurality of data stream storage areas, and a buffer; a first storage information memory for holding first storage information a processing unit, and a data storage controller. The data storage controller, for each received amount of data, receives the identity portion of the amount of data and performs a storage operation based on the identity portion.
Legal claims defining the scope of protection, as filed with the USPTO.
1. Data transmission apparatus for transmitting data from a plurality of data streams sent over a data channel, the apparatus comprising: a data memory for storing data to be transmitted; a data storage control memory for storing, for each data stream, a definition of a corresponding storage block in the data memory; a data transmission controller for generating a transmission control signal indicating one of the data streams for transmission; a data transmitter for receiving the transmission control signal, accessing the data storage control memory to determine a storage block corresponding to the said data stream for transmission, transmitting an amount of data from that storage block, and, if all data has been transmitted from that storage block, generating a block done indication for that block; and a memory controller responsive to a block done indication for a storage block to allocate to the data stream corresponding to that storage block another storage block in the data memory by storing, for that data stream, a definition of the other storage block in the data storage control memory.
2. Data transmission apparatus as claimed in claim 1 , wherein the data transmitter is provided by dedicated circuitry on an integrated circuit.
3. Data transmission apparatus as claimed in claim 1 , wherein the memory controller is provided by the central processing unit of an integrated circuit.
4. Data transmission apparatus as claimed in claim 1 , wherein the data transmitter and the memory controller are each provided by separate processing circuitry, the separate circuitry of the data transmitter and the memory controller being formed on a same integrated circuit.
5. Data transmission apparatus as claimed in claim 2 , wherein at least part of the data memory is on the integrated circuit.
6. Data transmission apparatus as claimed in claim 1 , wherein each storage block is a contiguous set of memory locations.
7. Data transmission apparatus as claimed in claim 6 , wherein the said definition of a storage block comprises an end memory address and the length of the storage block.
8. Data transmission apparatus as claimed in claim 6 , wherein the storage blocks are of differing sizes.
9. Data transmission apparatus as claimed in claim 1 , wherein the data storage control memory stores first error check information for at least one of the data streams, and before transmitting an amount of data from that data stream, the data transmitter performs an error check calculation using the first error check information and the contents of the amount of data to calculate second error check information and stores the second error check information in the data control memory to replace the first error check information.
10. Data transmission apparatus as claimed in claim 9 , wherein the data transmitter transmits the stored error check information on completing transmission of all data from a data stream.
11. Data transmission apparatus as claimed in claim 10 , wherein if the data transmitter determines transmission of all data from a data steam has been completed it generates a block done indication of a second type, in response to which the memory controller does not allocate another storage block to the data stream.
12. Data transmission apparatus as claimed in claim 1 , wherein the memory controller maintains a list of storage blocks available for allocation.
13. Data transmission apparatus as claimed in claim 1 , wherein the data storage control memory stores for each data stream an indication of a location in the data memory of the data which the data transmitter is next to transmit for that data stream.
14. Data transmission apparatus as claimed in claim 1 , wherein the data memory is provided by at least two discrete memory units.
15. Data transmission apparatus as claimed in claim 1 , wherein the amount of data is 384 bits.
16. Data transmission apparatus as claimed in claim 1 , wherein each amount of data is transmitted in the form of an ATM cell.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 6, 1999
December 9, 2003
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