A semiconductor device and a method for constructing a semiconductor device is disclosed. A deep trench isolation structure (108) is formed proximate a surface of a semiconductor substrate (106). A deep trench plug (122) layer is deposited within the deep trench isolation structure (108). A shallow trench isolation structure (130) is formed where the deep trench isolation structure (108) meets the surface of the semiconductor substrate (106). A shallow trench plug layer (133) is deposited within the shallow trench isolation structure (130).
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for constructing a semiconductor device, the method comprising: providing a semiconductor substrate comprising an inner substrate, a buried insulator layer, and an outer substrate; forming a deep trench isolation through said buried insulator layer; depositing a deep trench plug layer within the deep trench isolation structure; forming a shallow trench isolation structure where the deep trench isolation structure meets the surface of the semiconductor substrate; and depositing a shallow trench plug layer within the shallow trench isolation structure.
2. The method of claim 1 , wherein the deep trench plug layer comprises polycrystalline silicon.
3. The method of claim 1 , further comprising forming a channel stop region by performing an ion implantation into the semiconductor substrate through the deep trench isolation structure.
4. The method of claim 1 , wherein the deep trench isolation structure has a depth of at least approximately two microns.
5. The method of claim 1 , wherein the shallow trench isolation structure has a depth of less than approximately two microns.
6. The method of claim 1 , further comprising: growing a first liner layer comprising silicon dioxide on an inner surface of the deep trench isolation structure; and depositing a second liner layer comprising silicon nitride outwardly from the first liner layer.
7. The method of claim 1 , wherein depositing the deep trench plug layer occurs prior to forming the shallow trench isolation structure.
8. The method of claim 1 , further comprising: growing a liner layer on an inner surface of the deep trench isolation structure; and over-etching the liner layer to form the shallow trench isolation structure.
9. The method of claim 1 , wherein forming the shallow trench isolation structure occurs prior to depositing the deep trench plug layer.
10. The method of claim 1 , further comprising: depositing a resist layer within the deep trench isolation structure to form a resist plug; and forming the shallow trench isolation structure proximate the resist plug.
11. The method of claim 1 , wherein the deep trench isolation structure is faceted.
12. A method for constructing a semiconductor device, the method comprising: providing a semiconductor substrate comprising an inner substrate, a buried insulator, and an outer substrate; forming a shallow trench isolation structure proximate a surface of a semiconductor substrate; etching the shallow trench isolation structure to form a deep trench isolation structure where the shallow trench isolation structure meets the surface of the semiconductor substrate and where a bottom surface of the deep trench isolation structure comprises said buried insulator; depositing a deep trench plug layer within the deep trench isolation structure; depositing a shallow trench plug layer within the shallow trench isolation structure.
13. The method of claim 12 , wherein the deep trench plug layer comprises polycrystalline silicon.
14. The method of claim 13 , further comprising forming a channel stop region by performing an ion implantation into the semiconductor substrate through the deep trench isolation structure.
15. The method of claim 12 , wherein the deep trench isolation structure has a depth of at least approximately two microns.
16. The method of claim 12 , wherein the shallow trench isolation structure has a depth of less than approximately two microns.
17. A semiconductor device, comprising: a semiconductor substrate comprising an inner substrate, a buried insulator layer, and an outer substrate, a surface of the semiconductor substrate defining a deep trench isolation structure formed through said buried insulator layer and a shallow trench isolation structure, the deep trench isolation structure meeting the surface of the semiconductor substrate where the shallow trench isolation structure meets the surface of the semiconductor substrate; a deep trench plug deposited within the deep trench isolation structure; and a shallow trench plug deposited within the shallow trench isolation structure.
18. The semiconductor device of claim 17 , wherein the deep trench plug comprises polycrystalline silicon.
19. The semiconductor device of claim 17 , further comprising a channel stop region proximate the deep trench isolation structure.
20. The semiconductor device of claim 17 , wherein the deep trench isolation structure has a depth of at least approximately two microns.
21. The semiconductor device of claim 17 , wherein the shallow trench isolation structure has a depth of less than approximately two microns.
22. The semiconductor device of claim 17 , further comprising: a first liner layer comprising silicon dioxide formed on an inner surface of the deep trench isolation structure; and a second liner layer comprising silicon nitride deposited outwardly from the first liner layer.
23. The semiconductor device of claim 17 , further comprising a liner layer on an inner surface of the deep trench isolation structure, the liner layer over-etched to form the shallow trench isolation structure.
24. The semiconductor device of claim 17 , wherein the deep trench isolation structure is faceted.
25. A method for constructing a semiconductor device, the method comprising: providing a semiconductor substrate comprising an inner substrate, a buried insulator layer, and an outer substrate; forming a deep trench isolation structure through the buried insulator layer wherein the deep trench structure has a depth of approximately 2 microns; depositing a deep trench plug layer comprising polycrystalline silicon within the deep trench isolation structure; forming a channel stop region by performing an ion implantation into the semiconductor substrate through the deep trench isolation structure; growing a first liner layer comprising silicon dioxide on an inner surface of the deep trench isolation structure; depositing a second liner layer comprising silicon nitride outwardly from the first liner layer; over-etching the first liner layer and the second liner layer to form a shallow trench isolation structure where the deep trench isolation structure meets the surface of the semiconductor substrate, the shallow trench isolation structure having a depth of approximately 0.3 to 0.5 microns; and depositing a shallow trench plug layer within the shallow trench isolation structure.
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December 14, 2001
December 23, 2003
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