A sensing circuit. The circuit includes an integrator to sense charge release from a passive electronic device and a comparator to interpret the charge release as one of at least two data states. The circuit also includes a compensation module to generate a compensation signal as needed and a direct-timing module to time a period of integrator sensing based upon a predefined time period.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method to read information from a selected ferroelectric memory cell of a memory array, comprising: sensing charge from the selected ferroelectric memory cell during a first sensing interval to generate a first signal; and determining if a level of a reference signal is substantially equal to a level of the first signal during a second sensing interval.
2. The method of claim 1 , further comprising generating an output signal if the reference signal reaches a level substantially equal to a level of the first signal.
3. The method of claim 1 , further comprising comparing a level of the output signal to a threshold value to determine the data state of information stored in selected memory cell.
4. The method of claim 1 , sensing charge further comprising sensing charge during a first interval, wherein the first sensing interval ends when the level of the reference signal reaches a predetermined level.
5. The method of claim 1 , further comprising generating an output signal if a predetermined time period expires.
6. A device, comprising: a ferroelectric memory array; and a controller to controlling sensing intervals for cells of the ferroelectric memory array to compensate for residual charge from unselected cells.
7. The device of claim 6 , the ferroelectric memory array further comprising a polymer ferroelectric memory array.
8. The device of claim 6 , the controller further comprising a digital part and an analog part.
9. A method of reading a memory cell, the method comprising: sensing a first signal level from a ferroelectric memory cell in a first sensing interval, wherein the first sensing interval ends when a reference signal reaches a predetermined level; and generating an output signal when the reference signal has reached a level substantially equal to a level of the first signal in a second sensing interval.
10. The method of claim 9 , sensing a first signal level further comprising sensing a first voltage level from a ferroelectric memory cell.
11. The method of claim 9 , sensing a first signal level further comprising sensing a first signal level when the reference signal level becomes substantially equal to a threshold signal level.
12. The method of claim 10 , generating an output signal further comprising determining when a reference voltage has reached a level substantially equal to the first voltage level.
13. The method of claim 9 , generating an output signal further comprising determining if either a reference signal has reached the first signal level or a timeout has occurred.
14. The method of claim 9 , generating an output signal further comprising sensing a second signal from the ferroelectric memory cell.
15. The method of claim 14 , sensing a second voltage level further comprising sensing a second signal level in a second sensing interval, wherein the second sensing interval is longer than the first.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 14, 2003
December 23, 2003
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