Semiconductor memory and method for applying voltage to semiconductor memory device

1. A semiconductor memory comprising: a semiconductor memory device including a first transistor and a second transistor formed on a well, said first transistor having a tunnel oxide film, a floating gate, a drain, a source connected to a source line and a control gate connected to a control word line, said second transistor having a source, a drain connected to a data line and a gate connected to a select word line, and said drain of said first transistor being connected to said source of said second transistor; a first pulse generation circuit for outputting a pulse signal in injecting electrons into said floating gate of said first transistor; a first delay circuit for receiving said pulse signal from said first pulse generation circuit and outputting a first delay signal by delaying said pulse signal; a second delay circuit for receiving said first delay signal from said first delay circuit and outputting a second delay signal by delaying said first delay signal; a third delay circuit for receiving said second delay signal from said second delay circuit and outputting a third delay signal by delaying said second delay signal; a control word line driver circuit for changing potential of said control word line to a given voltage in response to said first delay signal received from said first delay circuit; a well driver circuit for changing potential of said well to a given voltage in response to said second delay signal received from said second delay circuit; and a source line driver circuit for changing potential of said source line to a given potential in response to said third delay signal received from said third delay circuit.

2. A semiconductor memory comprising: a semiconductor memory device including a first transistor and a second transistor formed on a well, said first transistor having a tunnel oxide film, a floating gate, a drain, a source connected to a source line and a control gate connected to a control word line, said second transistor having a source, a drain connected to a data line and a gate connected to a select word line, and said drain of said first transistor being connected to said source of said second transistor; a second pulse generation circuit for outputting a pulse signal in extracting electrons from said floating gate of said first transistor; a fourth delay circuit for receiving said pulse signal from said second pulse generation circuit and outputting a fourth delay signal by delaying said pulse signal; a fifth delay circuit for receiving said fourth delay signal from said fourth delay circuit and outputting a fifth delay signal by delaying said fourth delay signal; a control word line driver circuit for changing potential of said control word line to a given voltage in response to said fourth delay signal received from said fourth delay circuit; and a well driver circuit for changing potential of said well to a given voltage in response to said fifth delay signal received from said fifth delay circuit.

3. The semiconductor memory of claim 1 or 2 , wherein said gate of said second transistor is a first gate interconnect layer that is formed simultaneously with and from an identical interconnect layer with said floating gate of said first transistor.

4. The semiconductor memory of claim 1 or 2 , wherein said gate of said second transistor is obtained by connecting a first gate interconnect layer to a second gate interconnect layer, said first gate interconnect layer being formed simultaneously with and from an identical interconnect layer with said floating gate of said first transistor, and said second gate interconnect layer being formed simultaneously with and from an identical interconnect layer with said control gate of said first transistor.

5. A method for applying a voltage to a semiconductor memory device, said semiconductor memory device including a first transistor that is formed on a well and has a tunnel oxide film, a floating gate, a drain, a source connected to a source line and a control gate connected to a control word line; and a second transistor that is formed on said well and has a source, a drain connected to a data line and a gate connected to a select word line, said drain of said first transistor being connected to said source of said second transistor, said method comprising, for injecting electrons into said floating gate of said first transistor: a first step of changing potential of said control word line to a given voltage; a second step of changing potential of said well to a given voltage after changing the potential of said control word line in the first step; and a third step of changing potential of said source line to a given voltage after changing the potential of said well in the second step.

6. A method for applying a voltage to a semiconductor memory device, said semiconductor memory device including a first transistor that is formed on a well and has a tunnel oxide film, a floating gate, a drain, a source connected to a source line and a control gate connected to a control word line; and a second transistor that is formed on said well and has a source, a drain connected to a data line and a gate connected to a select word line, said drain of said first transistor being connected to said source of said second transistor, said method comprising, for extracting electrons from said floating gate of said first transistor: a first step of changing potential of said control word line to a given voltage; and a second step of changing potential of said well to a given voltage after changing the potential of said control word line in the fourth step.