The present invention is a method and apparatus for reducing processing overhead using a stream data reassembly mechanism and at least one data buffer. The present invention pre-processes incoming frames before delivering the frames to system memory. When a first packet of an data stream is received, the data from the packet is placed into a data buffer. Information about the first packet is stored in a logical channel descriptor (LCD) to indicate that data exists in the current data buffer. As each subsequent packet in the data stream is received, the reassembly mechanism removes extraneous transmission data from the packet and checks the CRC of each trailer to qualify the data within the packet. After the data is qualified, the reassembly mechanism stores the data portion of the packet in the data buffer. This preprocessing of each packet continues until a predetermined condition is met. Once a predetermined condition is met, the reassembly mechanism will make the contents of the buffer available to the system. The reassembly may optionally associate a direct memory access (DMA) descriptor with the buffer and burst the contents of the buffer into system memory. The reassembly mechanism of the present invention thereby reduces the amount of data reception interrupts processed by the system and can also reduce the number of direct memory access data transfer across the system bus.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus comprising: a processor; a memory coupled to the processor; means for receiving cells of transmitted frames from a network to which said apparatus is connected; means for storing said cells in a data buffer; means for monitoring for an end of frame signal; means for determining whether an error has occurred within the plurality of cells when an end of frame signal is received; means for comparing the length of data in the data buffer with a threshold if an end of frame signal has not been received and an error has not occurred; means for allocating a new buffer if the length of the data in the buffer is greater than the threshold; means for setting the new data store location at the end of the data if the length of the data in the buffer is not greater than the threshold; means, when an error is identified with a received cell, for: setting the end of the data in the data buffer equal to the already received data in the buffer minus the length of the cells of the frame within which the error is identified; surfacing the data buffer; indicating an error; and allocating a new data buffer; a reassembly mechanism that reassembles a plurality of received cells into a plurality of frames; and means for surfacing more than one of the plurality of frames from the buffer at a time to the processor.
2. The apparatus of claim 1 wherein the reassembly mechanism further comprises at least one buffer having a length of at least two frames, the means for resurfacing periodically surfacing the contents of the at least one buffer to the processor.
3. The apparatus of claim 1 wherein the plurality of cells are asynchronous transfer mode cells transmitted via an asynchronous transfer mode network.
4. The apparatus of claim 1 further comprising means for notifying the processor when the more than one of the plurality of frames of data is surfaced at a time.
5. The apparatus of claim 2 wherein the length of the at least one buffer is the length of a plurality of frames.
6. The apparatus of claim 2 wherein each of the plurality of frames comprises at least one cell, the reassembly mechanism placing the at least one cell into the at least one buffer when the at least one cell has been received.
7. The apparatus of claim 2 wherein said means for surfacing surfaces the at least one buffer when the at least one buffer is full, and wherein the reassembly mechanism allocates at least one new buffer when the at least one buffer is surfaced.
8. The apparatus of claim 1 wherein the reassembly mechanism checks each frame of the plurality of frames of data to see if an error has occurred.
9. The apparatus of claim 8 wherein the reassembly mechanism indicates an error to the processor when an error has occurred.
10. The apparatus of claim 9 wherein the reassembly mechanism automatically surfaces the plurality of frames of data when an error has occurred.
11. The apparatus of claim 1 wherein each frame of the plurality of frames contains information from one of a plurality of different streams, the reassembly mechanism further comprising a plurality of buffers, each of the plurality of buffers being uniquely assigned to one of the plurality of different streams, the means for receiving including means for selectively placing each of the plurality of cells into one of the plurality of buffers that has been uniquely assigned to a particular one of the plurality of different streams from which each of the plurality of cells came.
12. The apparatus of claim 1 wherein the means for surfacing transfers the contents of the at least one buffer to the memory by performing a direct memory access.
13. The apparatus of claim 1 wherein at least one of the plurality of cells contains a data stream content indicator and the means for surfacing surfaces the at least one buffer upon receipt of the data stream content indicator.
14. The apparatus of claim 13 wherein the data stream content indicator comprises an MPEG splice point.
15. The apparatus of claim 13 wherein the data stream content indicator comprises a discontinuity indicator.
16. An apparatus comprising: a processor; a memory coupled to the processor; and a reassembly mechanism residing in the memory and being executed by the processor, the reassembly mechanism comprising: at least one buffer having a length of at least two frames; means for receiving a plurality of asynchronous transfer mode cells and placing the plurality of asynchronous transfer mode cells into the at least one buffer; means for checking each received frame of said plurality of frames for an occurrence of an error; means, responsive to a determination that an error has occurred in a received frame, for: setting the end of the data in the data buffer equal to the already received data in the buffer minus the length of the cells of the frame within which the error occurred; surfacing the data buffer, wherein all previous frames in said at least one buffer are immediately surfaced and the received frame causing said error is not surfaced; indicating an error; and allocating a new data buffer; and means for otherwise surfacing the at least one buffer only when said at least one buffer contains at least two frames.
17. The apparatus of claim 16 wherein each cell of the plurality of cells is from one of a plurality of different streams, the reassembly mechanism further comprising a plurality of buffers, each of the plurality of buffers being uniquely assigned to one of the plurality of different streams, the reassembly mechanism selectively placing each of the plurality of cells into one of the plurality of buffers that has been uniquely assigned to that one of a plurality of different streams from which each of the plurality of cells came.
18. The apparatus of claim 16 wherein the length of the at least one buffer is the length of a plurality of frames.
19. The apparatus of claim 16 wherein the reassembly mechanism indicates an error to the processor if an error has occurred.
20. The apparatus of claim 16 wherein the reassembly mechanism surfaces the plurality of frames of data if an error has occurred.
21. The apparatus of claim 16 wherein the reassembly mechanism surfaces the at least one buffer when the at least one buffer is full, and automatically allocates at least one new buffer while surfacing the at least one buffer.
22. The apparatus of claim 16 wherein the reassembly mechanism transfers the contents of the at least one buffer to the memory by performing a direct memory access.
23. The apparatus of claim 16 wherein at least one of the plurality of cells contains a data stream content indicator and the reassembly mechanism surfaces the at least one buffer upon receipt of the data stream content indicator.
24. The apparatus of claim 23 wherein the data stream content indicator comprises an MPEG splice point.
25. An apparatus comprising: a processor coupled to a network and receiving a plurality of frames of data from the network, each frame of the plurality of frames of data being from one of a plurality of different streams; a memory coupled to the processor; and a reassembly mechanism residing in the memory and being executed by the processor, the reassembly mechanism comprising a plurality of buffers, each of the plurality of buffers being uniquely assigned to one of the plurality of different streams, the reassembly mechanism placing each frame into the buffer that has been uniquely assigned to a particular one of the plurality of different streams from which the frame came, each of the plurality of buffers having a length of at least two frames, said reassembly mechanism including: means for receiving said plurality of cells; means for storing data from each received cell into a data buffer; means for checking whether an end of frame has occurred; means for comparing the length of the data with a threshold if an end of frame has not occurred; means for setting a new data store location at the end of the data if the length of the data in the buffer is less than the threshold; means for allocating a new buffer if the length of the data in the buffer is greater than the threshold; means, when an error is identified with a received cell, for: setting the end of the data in the data buffer equal to the already received data in the buffer minus the length of the cells of the frame within which error is identified; surfacing the data buffer; indicating an error; and allocating a new data buffer; and means for periodically surfacing each buffer of the plurality of buffers to the processor, wherein a plurality of frames of a particular one of said plurality of different streams is surface at the same time.
26. The apparatus of claim 25 wherein the reassembly mechanism notifies the processor when each buffer of the plurality of buffers is surfaced.
27. The apparatus of claim 25 wherein the reassembly mechanism checks each frame to see if an error has occurred.
28. The apparatus of claim 27 wherein the reassembly mechanism surfaces the buffer that has been uniquely assigned to a particular one of a plurality of different streams from which the frame with the error came.
29. The apparatus of claim 27 wherein the frame with the error is not surfaced.
30. The apparatus of claim 25 wherein the reassembly mechanism surfaces at least one of the plurality of buffers when the at least one of the plurality of buffers is full, and wherein the reassembly mechanism allocates a new buffer, the new buffer being uniquely assigned to the one of the plurality of different streams to which the surfaced buffer was assigned.
31. A method for receiving data from a network, the method comprising the steps of: receiving cells containing data of a plurality of transmitted frames; associating a logical channel descriptor with the each cell, by: extracting a virtual path indicator and virtual circuit indicator from a received cell; and translating the virtual path indicator and virtual circuit indicator into the logical channel descriptor; storing each cell in a buffer that uniquely corresponds to the logical channel descriptor; updating the logical channel descriptor; reforming a plurality of said transmitted frames from said cells; and when an error is identified with a received cell, setting the end of the data in the data buffer equal to the already received data in the buffer minus the length of the cells of the frame within which the cell with said error belongs; surfacing the data buffer; indicating an error; and allocating a new data buffer; surfacing multiple ones of said transmitted frames at a same time from within said buffer to a receiving processor.
32. The method of claim 31 wherein the step of storing the cell in a buffer that uniquely corresponds to the logical channel descriptor further includes the steps of: reading the state of the logical channel descriptor; and using an existing data buffer pointer that uniquely corresponds to the logical channel descriptor to store the data in the buffer if the state of the logical channel descriptor indicates that the buffer is in progress.
33. The method of claim 32 wherein the step of using an existing data buffer pointer further includes the step of obtaining a new data buffer pointer that uniquely corresponds to the logical channel descriptor if the logical channel descriptor indicates that the buffer is not in progress.
34. A method for surfacing frames that are comprised of a plurality of cells, the method comprising the steps of: receiving said plurality of cells; storing data from each received cell into a data buffer; checking whether an end of frame has occurred; comparing the length of the data with a threshold if an end of frame has not occurred; setting a new data store location at the end of the data if the length of the data in the buffer is less than the threshold; allocating a new buffer if the length of the data in the buffer is greater than the threshold; when an error is identified within a received cell, setting the end of the data in the data buffer equal to the already received data in the buffer minus the length of the frame just received; surfacing the data buffer; indicating an error; and allocating a new data buffer; and surfacing the buffer, wherein multiple frames within said buffer are surfaced at the same time to a receiving processor.
35. The method of claim 34 wherein the step of checking to see if an end of frame has occurred further comprises the step of checking a user indicate bit to see if an error has occurred.
36. The method of claim 34 wherein the step of checking to see if an end of frame has occurred further comprises the step of checking to see if an error has occurred if an end of frame has occurred.
37. The method of claim 35 wherein the step of checking to see if an error has occurred further comprises the step of comparing the length of the data stream and the length of the data stream that has been received to see if an error has occurred.
38. The method of claim 35 wherein the step of checking to see if an error has occurred further comprises the step of checking a CRC 32 bit to see if an error has occurred.
39. A method for surfacing frames that are comprised of a plurality of cells, the method comprising the steps of: receiving said plurality of cells; storing said plurality of cells in a data buffer; monitoring for an end of frame signal; determining whether an error has occurred within the plurality of cells when an end of frame signal is received; when an error has occurred, setting the end of the data in the data buffer equal to the already received data in the buffer minus the length of the frame just received; surfacing the data buffer; indicating an error; and allocating a new data buffer; comparing the length of data in the data buffer with a threshold if an end of frame signal has not been received and an error has not occurred; allocating a new buffer if the length of the data in the buffer is greater than the threshold surfacing the buffer wherein multiple ones of said plurality of frames are surface at the same time; and setting the new data store location at the end of the data if the length of the data in the buffer is not greater than the threshold.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 9, 1998
December 23, 2003
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.