In a method for computer-aided design of a circuit, a hardware description code of the circuit is created using logical circuit blocks, each circuit block being allocated a supply voltage. The hardware description code is transformed into a net list that contains logical cells and their connections. A specific supply voltage is assigned to each cell by a unique identifier. Afterward, a time sequence analysis of the circuit is performed taking account of the identifiers of the cells.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for computer-aided design of a circuit having sections with different supply voltages, which comprises the steps of: creating a hardware description code of the circuit using logical circuit blocks; allocating a supply voltage to each of the logical circuit blocks; transforming the hardware description code into a net list containing logical cells and related connections, each of the logical cells corresponding to a cell type to which is added a unique identifier of the supply voltage to which a logical cell is assigned; assigning a connection attribute to each input and to each output of the logical cell; during the transforming step, the output of a first logical cell to be connected to the input of a second logical cell only when the output of the first logical cell and the input of the second logical cell have identical connection attributes; effecting an allocation of the connection attributes for inputs and outputs according to a predetermined assignment specification between a set of the identifiers and a set of the connection attributes; and carrying out an analysis of the circuit on a basis of the net list taking account of identifiers of the logical cells.
2. The method according to claim 1 , which comprises incorporating a level shifter cell between two of the logical cells having different identifiers.
3. The method according to claim 1 , which comprises assigning a specific identifier exactly one of the connection attributes which is assigned only to the specific identifier.
4. The method according to claim 1 , which comprises assigning one and the same connection attribute to a plurality of different identifiers.
5. The method according to claim 1 , which comprises during the transforming step, incorporating automatically a level shifter cell between the output of the first logical cell and the input of the second logical cell, provided that the connection attribute assigned to the output of the first logical cell is not identical to the connection attribute assigned to the input of the second logical cell.
6. A method for computer-aided design of a circuit having sections with different supply voltages, which comprises: creating a hardware description code of the circuit using logical circuit blocks; allocating a supply voltage to each of the logical circuit blocks; transforming the hardware description code into a net list containing logical cells and related connections, each of the logical cells corresponding to a cell type to which is added a unique identifier of the supply voltage to which a logical cell is assigned; carrying out an analysis of the circuit on a basis of the net list taking account of identifiers of the logical cells; during the carrying out step, performing a calculation step for determining signal transfer times within the logical cells having different identifiers, and for this purpose, accessing identifier-dependent technology information items with respect to the logical cells, the information items being contained in a technology cell library; choosing a reference voltage; transforming the identifier-dependent technology information items of the logical cells as a function of the reference voltage chosen; and carrying out the calculation step for the logical cells with the different identifiers using transformed technology information items and the reference voltage chosen.
7. The method according to claim 6 , which comprises providing identifier-dependent derating parameters in the technology cell library.
8. The method according to claim 6 , which comprises calculating a transformed derating parameter of a cell Z according to an equation k n (Z) (Ubas(Z)/Uref)*k(Z), where Ubas is the supply voltage assigned to the cell, k(Z) is the transformed derating parameter of the cell Z for the supply voltage and Uref is the reference voltage.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 4, 2002
December 23, 2003
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.