A nonvolatile semiconductor memory includes first and second nonvolatile memory banks, a data-line for read, a data-line for program and verify, a sense amplifier for read, a sense amplifier for program and verify, and a program circuit. The data-lines are arranged in a region between the first and second nonvolatile memory banks, and selectively connected to the bit-lines of the first and second nonvolatile memory banks. The sense amplifier for read is connected to the data-line for read. The sense amplifier for program and verify and the program circuit are connected to the data-line for program and verify.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A nonvolatile semiconductor memory comprising: first and second nonvolatile memory banks; a data-line for read and a data-line for program and verify which are arranged in a region between said first and second nonvolatile memory banks and selectively connected to bit-lines of said first and second nonvolatile memory banks, said data-line for read and said data-line for program and verify being shared between said first and second nonvolatile memory banks; a sense amplifier for read connected to said data-line for read; a sense amplifier for program and verify connected to said data-line for program and verify; and a program circuit connected to said data-line for program and verify.
2. A nonvolatile semiconductor memory comprising: first and second nonvolatile memory banks; data-lines for read and data-lines for program and verify which are arranged in a region between said first and second nonvolatile memory banks and selectively connected to bit-lines of said first and second nonvolatile memory banks, the number of data-lines for read is N 1 , and the number of data-lines for program and verify is N 2 that is smaller than N 1 ; sense amplifiers for read connected to said data-lines for read, the number of sense amplifiers for read is N 1 ; sense amplifiers for program and verify connected to said data-lines for program and verify, the number of sense amplifiers for program and verify is N 2 ; and a program circuit connected to said data-lines for program and verify.
3. A nonvolatile semiconductor memory comprising: first and second nonvolatile memory banks each having a drain wiring line of a memory cell transistor formed from a first metal layer; a data-line for read and a data-line for program and verify which are arranged in a region between said first and second nonvolatile memory banks and selectively connected to bit-lines of said first and second nonvolatile memory banks, said data-line for read and said data-line for program and verify being formed from a second metal layer, and the bit-lines of said first and second nonvolatile memory banks being selectively connected to said data-line for read and said data-line for program and verify via wiring lines formed from the first metal layer; a sense amplifier for read connected to said data-line for read; a sense amplifier for program and verify connected to said data-line for program and verify; and a program circuit connected to said data-line for program and verify.
4. A nonvolatile semiconductor memory comprising: first and second nonvolatile memory banks each having a drain wiring line of a memory cell transistor formed from a first metal layer; a data-line for read and a data-line for program and verify which are arranged in a region between said first and second nonvolatile memory banks and selectively connected to bit-lines of said first and second nonvolatile memory banks, said data-line for read and said data-line for program and verify being formed from a third metal layer, and the bit-lines of said first and second nonvolatile memory banks being selectively connected to said data-line for read and said data-line for program and verify via wiring lines formed from a second metal layer; a sense amplifier for read connected to said data-line for read; a sense amplifier for program and verify connected to said data-line for program and verify; and a program circuit connected to said data-line for program and verify.
5. A nonvolatile semiconductor memory comprising: first and second nonvolatile memory banks each having a drain wiring line of a memory cell transistor formed from a first metal layer; a data-line for read and a data-line for program and verify which are arranged in a region between said first and second nonvolatile memory banks and selectively connected to bit-lines of said first and second nonvolatile memory banks, said data-line for program and verify being formed from the first metal layer, said data-line for read being formed from a third metal layer, a wiring line which connects the bit-lines of said first and second nonvolatile memory banks, and said data-line for program and verify being formed from a first or second metal layer, and said data-line for read being arranged over/above said data-line for program and verify; a sense amplifier for read connected to said data-line for read; a sense amplifier for program and verify connected to said data-line for program and verify; and a program circuit connected to said data-line for program and verify.
6. A nonvolatile semiconductor memory comprising: a nonvolatile memory block matrix in which a plurality of nonvolatile memory blocks are arrayed in a matrix in X and Y directions, each of said plurality of nonvolatile memory blocks having a first nonvolatile memory element, a first word-line and a first bit-line connected to said first nonvolatile memory element, a first row decoder connected to said first word-line, a first column decoder connected to said first bit-line, and a block decoder connected to said first row decoder and said first column decoder; a second word-line connected to said first row decoder; a second bit-line connected to said first column decoder; a second row decoder connected to said second word-line; second and third column decoders connected to said second bit-line; a first data-line connected to said second column decoder; a second data-line connected to said third column decoder; a first sense amplifier connected to said first data-line; and a second sense amplifier connected to said second data-line.
7. The memory according to claim 6 , wherein said first sense amplifier operates to read out memory data from a nonvolatile memory cell, and said second sense amplifier operates to verify whether program data is programmed in the nonvolatile semiconductor memory cell.
8. The memory according to claim 7 , wherein the number of first sense amplifiers is not less than the number of second sense amplifiers.
9. The memory according to claim 6 , which further comprises at least one redundancy nonvolatile memory block having a second nonvolatile memory element, a first redundancy word-line and a first redundancy bit-line connected to said second nonvolatile memory element, a first redundancy row decoder connected to said first redundancy word-line, a first redundancy column decoder connected to said first redundancy bit-line, and a redundancy block decoder connected to said first redundancy row decoder and said first redundancy column decoder, which further comprises a second redundancy word-line connected to said first redundancy row decoder, a second redundancy bit-line connected to said first redundancy column decoder, a second redundancy row decoder connected to said second redundancy word-line, and a second redundancy column decoder connected to said second redundancy bit-line, and in which said first data-line is connected to said first redundancy column decoder and said second data-line is connected to said second redundancy column decoder.
10. The memory according to claim 6 , in which said first sense amplifier comprises N M sense amplifier circuits, and which further comprises N data output buffers, N M latch circuits which latch outputs from said N M sense amplifier circuits, and a multiplexer which selects N 1 latch data from N M latch data output from said N M latch circuits.
11. The memory according to claim 6 , in which said first sense amplifier comprises (N M K) sense amplifier circuits, and which further comprises N data output buffers, (N M K) latch circuits which latch outputs from said (N M K) sense amplifier circuits, and a multiplexer which selects N 1 latch data from (N M K) latch data output from said (N M K) latch circuits.
12. The memory according to claim 11 , wherein the number of redundancy columns is K.
13. The memory according to claim 9 , which further comprises a first power switch which transfers a programming voltage when data are programmed into said nonvolatile memory or said redundancy nonvolatile memory, and a second power switch which transfers the programming voltage when data are programmed into said redundancy nonvolatile memory.
14. A nonvolatile semiconductor memory comprising: first and second nonvolatile memory banks, each of said first and second nonvolatile memory banks having a first word-line, a first row decoder connected to said first word-line, a first bit-line, and first and second column decoders connected to said first bit-line; nonvolatile memory block matrices which are respectively arranged in said first and second nonvolatile memory banks and have a plurality of nonvolatile memory blocks arrayed in a matrix in X and Y directions, each of said plurality of nonvolatile memory blocks having a first nonvolatile memory element, a second word-line and a second bit-line connected to said first nonvolatile memory element, a second row decoder connected to said first and second word-lines, a third column decoder connected to said first and second bit-lines, and a block decoder connected to said second row decoder and said third column decoder; a first data-line commonly connected to said first column decoder of said first nonvolatile memory bank and said first column decoder of said second nonvolatile memory bank; a second data-line connected to said second column decoder of said first nonvolatile memory bank and said second column decoder of said second nonvolatile memory bank; a first sense amplifier connected to said first data-line; and a second sense amplifier connected to said second data-line.
15. The memory according to claim 14 , wherein said first sense amplifier operates to read out memory data from a nonvolatile memory cell, and said second sense amplifier operates to verify whether program data is programmed in the nonvolatile semiconductor memory cell.
16. The memory according to claim 15 , wherein the number of first sense amplifiers is not less than the number of second sense amplifiers.
17. The memory according to claim 14 , which further comprises at least one redundancy nonvolatile memory block having a second nonvolatile memory element, a first redundancy word-line and a second redundancy bit-line connected to said second nonvolatile memory element, a first redundancy row decoder connected to said first redundancy word-line, a first redundancy column decoder connected to said first redundancy bit-line, and a redundancy block decoder connected to said first redundancy row decoder and said first redundancy column decoder, which further comprises a second redundancy word-line connected to said first redundancy row decoder, a third redundancy bit-line connected to said first redundancy column decoder, a second redundancy row decoder connected to said second redundancy word-line, and a second redundancy column decoder connected to said third redundancy bit-line, and in which said first data-line is connected to said first redundancy column decoder and said second data-line is connected to said second redundancy column decoder.
18. The memory according to claim 14 , wherein data in said nonvolatile memory element of said second nonvolatile memory bank is read out while data is programmed in said nonvolatile memory element of said first nonvolatile memory bank.
19. The memory according to claim 18 , which further comprises a program address buffer which holds an address of a nonvolatile memory element to be programmed, and a read buffer which transfers an address input to an address input terminal, and in which an address input to a bank including said nonvolatile memory element to be programmed is used as the program address.
20. The memory according to claim 18 , which further comprises a read word-line voltage generation circuit which generates a read word-line voltage, a program word-line voltage generation circuit which generates a program word-line voltage, and a program bit-line voltage generation circuit which generates a program bit-line voltage, and in which the program word-line voltage and the program bit-line voltage are applied to a bank including said nonvolatile memory element to be programmed, and the read word-line voltage is applied to a bank including no nonvolatile memory element to be programmed.
21. The memory according to claim 20 , in which said first sense amplifier comprises N M sense amplifier circuits, and which further comprises N data output buffers, N M latch circuits which latch outputs from said N M sense amplifier circuits, and a multiplexer which selects N 1 latch data from N M latch data output from said N M latch circuits.
22. The memory according to claim 20 , in which said first sense amplifier comprises (N M K) sense amplifier circuits, and which further comprises N data output buffers, (N M K) latch circuits which latch outputs from said (N M K) sense amplifier circuits, and a multiplexer which selects N 1 latch data from (N M K) latch data output from said (N M K) latch circuits.
23. The memory according to claim 22 , wherein the number of redundancy columns is K.
24. The memory according to claim 17 , which further comprises a first power switch which transfers a reprogram voltage when memory cell data in said nonvolatile memory bank is reprogrammed, and a second power switch which transfers the reprogram voltage when memory cell data in said redundancy nonvolatile memory block is reprogrammed, and in which said first power switch is selected when memory cell data in said redundancy nonvolatile memory block is reprogrammed.
25. A nonvolatile semiconductor memory comprising: a nonvolatile memory block matrix in which a plurality of nonvolatile memory blocks are arrayed in a matrix in X and Y directions, each of said plurality of memory blocks having a first nonvolatile memory element, a first redundancy nonvolatile memory element, a first word-line and a first bit-line connected to said first nonvolatile memory element, said first word-line and a first redundancy bit-line connected to said nonvolatile memory element, a first row decoder connected to said first word-line, a first column decoder connected to said first bit-line and said first redundancy bit-line, and a block decoder connected to said first row decoder and said first column decoder; a second word-line connected to said first row decoder; a second bit-line and a second redundancy bit-line connected to said first column decoder; a second row decoder connected to said second word-line; second and third column decoders connected to said second bit-line and said second redundancy bit-line; a first data-line and a first redundancy data-line connected to said second column decoder; a second data-line and a second redundancy data-line connected to said third column decoder; a first sense amplifier connected to said first data-line and said first redundancy data-line; and a second sense amplifier connected to said second data-line and said second redundancy data-line.
26. The memory according to claim 25 , wherein said first sense amplifier operates to read out memory data from a nonvolatile memory cell, and said second sense amplifier operates to verify whether program data is programmed in the nonvolatile semiconductor memory cell.
27. The memory according to claim 26 , wherein the number of first sense amplifiers is not less than the number of second sense amplifiers.
28. The memory according to claim 25 , which further comprises at least one redundancy nonvolatile memory block having a second nonvolatile memory element, a second redundancy nonvolatile memory element, a first redundancy word-line and a fourth redundancy bit-line connected to said second redundancy nonvolatile memory element, a first redundancy row decoder connected to said first redundancy word-line, a first redundancy column decoder connected to said first redundancy bit-line, and a redundancy block decoder connected to said first redundancy row decoder and said first redundancy column decoder, which further comprises a second redundancy word-line connected to said first redundancy row decoder, a fifth redundancy bit-line connected to said first redundancy column decoder, a second redundancy row decoder connected to said second redundancy word-line, and a second redundancy column decoder connected to said fifth redundancy bit-line, and in which said first data-line is connected to said second redundancy column decoder and said second data-line is connected to said third redundancy column decoder.
29. The memory according to claim 28 , which further comprises a first power switch which transfers a reprogram voltage when memory cell data in said nonvolatile memory block is reprogrammed, and a second power switch which transfers the reprogram voltage when memory cell data in said redundancy nonvolatile memory block is reprogrammed, and in which said first power switch is selected when memory cell data in said redundancy nonvolatile memory block is reprogrammed.
30. A nonvolatile semiconductor memory comprising: first and second nonvolatile memory banks, each of said first and second nonvolatile memory banks having a first word-line, a first row decoder connected to said first word-line, a first bit-line, a first redundancy bit-line, and first and second column decoders connected to said first bit-line and said first redundancy bit-line; nonvolatile memory block matrices which are respectively arranged in said first and second nonvolatile memory banks and have a plurality of nonvolatile memory blocks arrayed in a matrix in X and Y directions, each of said plurality of nonvolatile memory blocks having a first nonvolatile memory element, a first redundancy nonvolatile memory element, a second word-line and a second bit-line connected to said first nonvolatile memory element, a second word-line and a second redundancy bit-line connected to said first redundancy nonvolatile memory element, a second row decoder connected to said first and second word-lines, a third column decoder connected to said second bit-line and said second redundancy bit-line, and a block decoder connected to said second row decoder and said third column decoder; a first data-line commonly connected to said first column decoder of said first nonvolatile memory bank and said first column decoder of said second nonvolatile memory bank; a second data-line connected to said second column decoder of said first nonvolatile memory bank and said second column decoder of said second nonvolatile memory bank; a first sense amplifier connected to said first data-line; and a second sense amplifier connected to said second data-line.
31. The memory according to claim 30 , wherein said first sense amplifier operates to read out memory data from a nonvolatile memory cell, and said second sense amplifier operates to verify whether program data is programmed in the nonvolatile semiconductor memory cell.
32. The memory according to claim 31 , wherein the number of first sense amplifiers is not less than the number of second sense amplifiers.
33. The memory according to claim 30 , which further comprises at least one redundancy nonvolatile memory block having a second nonvolatile memory element, a second redundancy nonvolatile memory element, a first redundancy word-line and a fourth redundancy bit-line connected to said second redundancy nonvolatile memory element, a first redundancy row decoder connected to said first redundancy word-line, a first redundancy column decoder connected to said first redundancy bit-line, and a redundancy block decoder connected to said first redundancy row decoder and said first redundancy column decoder, which further comprises a second redundancy word-line connected to said first redundancy row decoder, a fifth redundancy bit-line connected to said first redundancy column decoder, a second redundancy row decoder connected to said second redundancy word-line, and a second redundancy column decoder connected to said fifth redundancy bit-line, and in which said first data-line is connected to said second redundancy column decoder and said second data-line is connected to said third redundancy column decoder.
34. The memory according to claim 30 , wherein data in said nonvolatile memory element of said second bank is read out while data is programmed in said nonvolatile memory element of said first bank.
35. The memory according to claim 34 , which further comprises a program address buffer which holds an address of a nonvolatile memory element to be programmed, and a read buffer which transfers an address input to an address input terminal, and in which an address input to a bank including said nonvolatile memory element to be programmed is used as the program address.
36. The memory according to claim 35 , which further comprises a read word-line voltage generation circuit which generates a read word-line voltage, a program word-line voltage generation circuit which generates a program word-line voltage, and a program bit-line voltage generation circuit which generates a program bit-line voltage, and in which the program word-line voltage and the program bit-line voltage are applied to a bank including said nonvolatile memory element to be programmed, and the read word-line voltage is applied to a bank including no nonvolatile memory element to be programmed.
37. The memory according to claim 36 , in which said first sense amplifier comprises N M sense amplifier circuits, and which further comprises N data output buffers, N M latch circuits which latch outputs from said N M sense amplifier circuits, and a multiplexer which selects N 1 latch data from N M latch data output from said N M latch circuits.
38. The memory according to claim 36 , in which said first sense amplifier comprises (N M K) sense amplifier circuits, and which further comprises N data output buffers, (N M K) latch circuits which latch outputs from said (N M K) sense amplifier circuits, and a multiplexer which selects N 1 latch data from (N M K) latch data output from said (N M K) latch circuits.
39. The memory according to claim 38 , wherein the number of redundancy columns is K.
40. The memory according to claim 39 , which further comprises a first power switch which transfers a reprogram voltage when memory cell data in said nonvolatile memory bank is reprogrammed, and a second power switch which transfers the reprogram voltage when memory cell data in said redundancy nonvolatile memory block is reprogrammed, and in which said first power switch is selected when memory cell data in said redundancy nonvolatile memory block is reprogrammed.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
August 30, 2002
December 30, 2003
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