An exemplary embodiment of the invention is a built-in self-test (BIST) method and apparatus for testing the logic circuits on an integrated circuit. Random test pattern data is generated by a random pattern generator. A random resistant fault analysis (RRFA) program is used to determine the weighting requirements, on a per channel basis, for testing the logic circuits. The weighting requirements from the RRFA program are applied to the random test pattern data resulting in weighted test pattern data. The weighted test pattern data is then programmably applied to the scan chain.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of testing an integrated circuit comprising logic circuits connected to a scan chain and a built in self-test circuit for testing said logic circuits, the method comprising: creating test pattern data for testing said integrated circuit by using a random pattern generator; using a random resistant fault analysis program to determine weighting requirements for testing a portion of said integrated circuit, said random resistant fault analysis program applying random patterns, to logic blocks and determining a number of faults per logic block for each random pattern, said weighting requirements determined in response to the number of faults per logic block for each random pattern; creating per channel weighting data based on said weighting requirements; generating weighted test pattern data in response to said test pattern data and said per channel weighting data; and, programmably applying said weighted test pattern data to the scan chain.
2. The method as recited in claim 1 , wherein each channel may have more than one set of said per channel weighting data.
3. The method as recited in claim 1 , wherein each channel may have more than one set of said weighted test pattern data.
4. The method as recited in claim 1 , wherein said weighted test pattern data is applied to each scan chain more than once.
5. The method as recited in claim 1 , wherein said weighting requirements are one of , or .
6. An integrated circuit, comprising logic circuits connected to a scan chain and self-test circuits for testing said logic circuits, said self-test circuits comprising: a random pattern generator for generating at least one random test pattern; a weighting circuit for applying said weighting requirements to said random test pattern resulting in a weighted random test pattern; a selection circuit responsive to random resistant fault analysis and providing said weighted random test pattern to said scan chain for scanning said weighted pattern to said logic circuits, said random resistant fault analysis applying random patterns to logic blocks and determining a number of faults per logic block for each random pattern, said weighting requirements determined in response to the number of faults per logic block for each random pattern.
7. The apparatus as recited in claim 6 , wherein each channel may have more than one set of said per channel weighting data.
8. The apparatus as recited in claim 6 , wherein each channel may have more than one set of said weighted test pattern data.
9. The apparatus as recited in claim 6 , wherein said weighted test pattern data is applied to each scan chain more than once.
10. The method as recited in claim 1 , wherein said weighting requirements are determined in response said random pattern generating a highest number of faults per logic block.
11. The apparatus as recited in claim 6 , wherein said weighting requirements are determined in response said random pattern generating a highest number of faults per logic block.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 27, 2000
December 30, 2003
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