A semiconductor device includes first and second polysilicon areas on a chip. The first polysilicon area corresponds to circuit elements of the semiconductor device. At least some of the first polysilicon corresponds to polysilicon gates. At least some of the second polysilicon area comprises contacts of the semiconductor device. Metal covers the polysilicon contacts.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: first polysilicon forming circuit elements of the semiconductor device on a chip, wherein at least some of the circuit elements comprise polysilicon gates; second polysilicon forming polysilicon pads of the semiconductor device on the chip, wherein at least one of the polysilicon pads is on the chip, is located distally from the circuit elements, and is unconnected from the circuit elements; and, metal pads covering the polysilicon pads.
2. The semiconductor device of claim 1 wherein the first and second polysilicon are formed on the chip so that there is no metal coupling between the first and second polysilicon.
3. The semiconductor device of claim 1 wherein each of the polysilicon gates is on the order of 0.35 in length.
4. The semiconductor device of claim 1 wherein the polysilicon gates are divided into at least first and second groups, wherein the polysilicon gates of the first group are intercoupled, wherein the polysilicon gates of the second group are intercoupled, and wherein each of the polysilicon gates is on the order of 0.35 microns in length.
5. The semiconductor device of claim 1 wherein at least three of the metal pads covering the polysilicon pads are probe pads, wherein a first of the probe pads comprises an input of the semiconductor device, wherein a second of the probe pads comprises an output of the semiconductor device, and wherein a third of the probe pads comprises a control of the semiconductor device.
6. The semiconductor device of claim 5 wherein each of at least six metal pads covers a corresponding polysilicon pad.
7. The semiconductor device of claim 6 wherein each of at least ten metal pads covers a corresponding polysilicon pad.
8. The semiconductor device of claim 6 wherein the chip has an area, and wherein the first and second polysilicon comprise between 13% and 16% of the area of the chip.
9. The semiconductor device of claim 8 wherein the first polysilicon comprises 1% or less of the area of the chip.
10. The semiconductor device of claim 6 wherein the chip has an area, and wherein the first and second polysilicon comprise substantially 14% of the area of the chip.
11. The semiconductor device of claim 10 wherein the first polysilicon comprises 1% or less of the area of the chip.
12. The semiconductor device of claim 1 wherein at least a portion of the polysilicon gates form a gate of a transistor, wherein the transistor comprises alternating source and drain regions, and wherein each polysilicon gate of the transistor is between a pair of adjacent source and drain regions.
13. The semiconductor device of claim 12 further comprising at least one polysilicon resistor.
14. The semiconductor device of claim 1 wherein the first polysilicon forms all of the circuit elements of the semiconductor device, and wherein all of the polysilicon pads of the semiconductor device are located distally from the circuit elements.
15. A semiconductor device chip comprising: a first transistor comprising gate regions and alternating source and drain regions, wherein each gate region of the first transistor is between a pair of adjacent source and drain regions, and wherein each gate region of the first transistor comprises polysilicon; a second transistor comprising gate regions and alternating source and drain regions, wherein each gate region of the second transistor is between a pair of adjacent source and drain regions, and wherein each gate region of the second transistor comprises polysilicon; a third transistor comprising gate regions and alternating source and drain regions, wherein each gate region of the third transistor is between a pair of adjacent source and drain regions, and wherein each gate region of the third transistor comprises polysilicon; a plurality of polysilicon resistors; a plurality of non-capacitor polysilicon pads; and, contacts covering the non-capacitor polysilicon pads.
16. The semiconductor device chip of claim 15 wherein the gate regions of the first, second, and third transistors, the polysilicon resistors, and the polysilicon pads are arranged so that there is substantially little RF coupling between (i) the polysilicon of the first, second, and third transistors and of the resistors and (ii) the polysilicon of the polysilicon pads.
17. The semiconductor device chip of claim 15 wherein the amount of polysilicon of the gate regions, polysilicon resistors, and polysilicon pads permits a polysilicon etch to operate so that the gate regions have substantially vertical walls.
18. The semiconductor device chip of claim 15 wherein each of the gate regions of each of the first, second, and third transistors is on the order of 0.35 in length.
19. The semiconductor device chip of claim 15 wherein the plurality of polysilicon pads comprises at least three polysilicon pads covered by a corresponding number of the contacts, wherein a first of the contacts comprises an input of the semiconductor device chip, wherein a second of the contacts comprises an output of the semiconductor device chip, and wherein a third of the contacts comprises a control terminal of the semiconductor device chip.
20. The semiconductor device chip of claim 19 wherein the plurality of polysilicon pads comprises at least six polysilicon pads.
21. The semiconductor device chip of claim 19 wherein the plurality of polysilicon pads comprises at least ten polysilicon pads.
22. The semiconductor device chip of claim 15 having an area, wherein the polysilicon of the gate regions, the resistors, and the polysilicon pads comprises between 13% and 16% of the area of the semiconductor device chip.
23. The semiconductor device chip of claim 22 wherein the polysilicon of the gate regions comprises less than 1% of the area of the semiconductor device chip.
24. The semiconductor device chip of claim 15 having an area, wherein the polysilicon of the gate regions, the resistors, and the polysilicon pads comprise substantially 14% of the area of the semiconductor device chip.
25. The semiconductor device chip of claim 24 wherein the polysilicon of the gate regions comprises less than 1% of the area of the semiconductor device chip.
26. A semiconductor device comprising: a transistor having a gate, a source, and a drain, wherein the gate comprises a polysilicon gate; at least one polysilicon pad laterally distal and electrically isolated from all circuit elements of the semiconductor device; and, a metal pad covering the polysilicon pad.
27. The semiconductor device of claim 26 wherein the polysilicon gate and the polysilicon pad is formed on the chip so that there is no metal coupling between the polysilicon gate and the polysilicon pad.
28. The semiconductor device of claim 26 wherein the polysilicon gate is on the order of 0.35 in length.
29. The semiconductor device of claim 27 wherein the at least one polysilicon pad comprises a first polysilicon pad, wherein the metal pad comprises a first metal pad, and wherein the semiconductor device further comprises second and third polysilicon pads and second and third metal pads covering the second and third polysilicon pads, respectively, wherein the first metal pad comprises an input of the semiconductor device, wherein the second metal pad comprises an output of the semiconductor device, and wherein the third metal pad comprises a control of the semiconductor device.
30. The semiconductor device of claim 26 wherein the chip has a chip area, wherein all polysilicon on the chip has a total polysilicon area, and wherein the total polysilicon area comprises between 13% and 16% of the chip area.
31. The semiconductor device of claim 30 wherein all polysilicon forming gates on the chip has a total gate polysilicon area, and wherein the total gate polysilicon area comprises 1% or less of the chip area.
32. The semiconductor device of claim 26 wherein the chip has a chip area, wherein all polysilicon on the chip has a total polysilicon area, and wherein the total polysilicon area comprises substantially 14% of the chip area.
33. The semiconductor device of claim 32 wherein all polysilicon forming gates on the chip has a total gate polysilicon area, and wherein the total gate polysilicon area comprises 1% or less of the chip area.
34. A semiconductor chip comprising: gate polysilicon forming at least one polysilicon gate; non-gate polysilicon forming polysilicon pads on the chip; and, metal pads covering the polysilicon pads, wherein the chip has a chip area, wherein the gate polysilicon and the non-gate polysilicon has a total polysilicon area, wherein the total polysilicon area comprises at least 13% of the chip area, wherein the gate polysilicon has a gate polysilicon area, and wherein the gate polysilicon area comprises 1% or less of the chip area.
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December 20, 2000
January 6, 2004
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