A static memory device that utilizes differential current bit line drivers to write information into the device's memory cells, and differential current sensing read amplifiers to read information from the cells. The drivers and amplifiers operate using limited differential current. The use of limited differential current, as opposed to voltages, reduces the power consumed by the device and increases the speed of read and write operations.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of writing data into a static memory device comprising the steps of: inputting data to be written into a memory cell, the memory cell being connected to first and second bit lines; generating first and second currents in response to the input data; and writing the first and second currents to the memory cell via the bit lines, wherein said first and second currents represent a value of the input data.
2. The method of claim 1 further comprising the step of biasing the bit lines to a predetermined voltage level when a write operation is not being performed.
3. The method of claim 1 further comprising the step of biasing the bit lines to a predetermined voltage level when a read operation or a write operation is not being performed.
4. The method of claim 2 wherein the predetermined voltage is smaller than a first voltage used to power the memory device, but more than half of the first voltage.
5. The method of claim 2 wherein the predetermined voltage is approximately fifty-five percent of the first voltage.
6. A method of writing data into a static memory device comprising the steps of: inputting data to be written into a memory cell, the memory cell being connected to first and second bit lines; generating first and second currents in response to the input data; and applying the first and second currents onto the bit lines, wherein said first and second currents represent a value of the input data or a tri-state condition and wherein said generating step comprises: switching in first and second adjustable resistive elements; and applying respective first and second voltages to the first and second first and second adjustable resistive elements.
7. The method of claim 6 further comprising the step of adjusting the first and second adjustable resistive elements.
8. A method of reading data from a static memory device comprising the steps of: sensing first and second currents from respective first and second bit lines connected to a memory cell of the device; converting the sensed first and second currents into a voltage level representing a logical value of a content of the cells; and latching the logical value until the next read operation is performed on the cell.
9. The method of claim 8 wherein said sensing step comprises: biasing the bit lines to a predetermined voltage; discharging one of the bit lines based on the content of the memory cell; and sensing the current on the bit lines.
10. The method of claim 8 wherein said sensing step comprises: biasing the bit lines to a predetermined voltage; charging one of the bit lines based on the content of the memory cell; and sensing the current on the bit lines.
11. A differential write driver for a static memory circuit, said write driver comprising: an input circuit connected to a memory cell via first and second bit lines, said input circuit inputting data to be written into a memory cell; and a current generating circuit connected to said input circuit, said current generating circuit generating first and second currents in response to the input data and applying the first and second currents to the memory cell via the bit lines, said first and second currents representing a value of the input data.
12. The write diver of claim 11 , further comprising a biasing circuit coupled to said bit lines, said biasing circuit biasing the bit lines to a predetermined voltage level when a write operation is not being performed.
13. The write driver of claim 12 , wherein the predetermined voltage is smaller than a first voltage used to power the driver, but more than half of the first voltage.
14. The write driver of claim 13 , wherein the predetermined voltage is approximately fifty-five percent of the first voltage.
15. The write driver of claim 11 further comprising a biasing circuit coupled to said bit lines, said biasing circuit biasing the bit lines to a predetermined voltage level when a read operation or a write operation is not being performed.
16. The write driver of claim 15 , wherein the predetermined voltage is smaller than a first voltage used to power the driver, but more than half of the first voltage.
17. The write driver of claim 16 , wherein the predetermined voltage is approximately fifty-five percent of the first voltage.
18. A differential write driver for a static memory circuit, said write driver comprising: an input circuit connected to a memory cell via first and second bit lines, said input circuit inputting data to be written into a memory cell; and a current generating circuit connected to said input circuit, said current generating circuit generating first and second currents in response to the input data and applying the first and second currents onto the bit lines, said first and second currents representing a value of the input data or a tri-state condition, wherein said current generating circuit comprises: a first adjustable resistive element connected to a first voltage, a resistance of said first adjustable resistive element being controllable by a first control signal; a second adjustable resistive element connected to a second voltage, a resistance of said second adjustable resistive element being controllable by a second control signal; a first switch for switching in the resistance of the first adjustable resistive element in response to a third control signal; and a second switch for switching in the resistance of the second adjustable resistive element in response to a fourth control signal, wherein said first voltage is applied to said first adjustable resistive element and said second voltage is applied to said second adjustable resistive element when said third and fourth control signals are received.
19. The write driver of claim 18 , wherein the fourth control signal is a complement of the third control signal.
20. The write driver of claim 19 , wherein said third control signal is an enable signal and the fourth control signal is a complement of the enable signal.
21. The write driver of claim 18 further comprising a current loop generating circuit for generating the first and second control signals based on a reference voltage and a resistance of said current loop generating circuit.
22. The write driver of claim 11 wherein said input circuit further comprises an input logic circuit for inputting the data and first and second control signals, wherein said first and second control signals are used to determine if a read or write operation is in progress.
23. A differential write driver for a static memory circuit, said write driver comprising: an input circuit connected to a memory cell via first and second bit lines, said input circuit inputting data to be written into a memory cell; a current generating circuit connected to said input circuit, said current generating circuit generating first and second currents in response to the input data and applying the first and second currents onto the bit lines, said first and second currents representing a value of the input data or a tri-state condition; and a biasing circuit comprising: a first resistive element coupled between a first voltage and the first bit line a second resistive element coupled between a second voltage and the second bit line; and a third resistive element coupled between the first and second bit lines, wherein said resistive elements are controlled to produce a predetermined voltage level on said bit lines when a write operation is not being performed.
24. The write driver of claim 23 , wherein said biasing circuit further comprises a bit line reference and said bit line reference is used to generate said predetermined voltage.
25. A current sensing receiver circuit for a static memory device comprising: a current sensing circuit connected to first and second bit lines, said current sensing circuit respectively sensing first and second currents from said first and second bit lines, said bit lines being connected to a memory cell of the device; and a conversion circuit coupled to said first and second currents, said conversion circuit converting the first and second currents into a voltage level representing a logical value of a content of the cell and latching the logical value until the next read operation is performed on the cell.
26. The current sensing receiver of claim 25 wherein said conversion circuit comprises a flip-flop circuit.
27. The current sensing receiver of claim 26 wherein the flip-flop circuit latches the logical value until the next read operation is performed on the cell.
28. The current sensing receiver of claim 25 wherein said conversion circuit comprises: a first latching circuit coupled to said first and second currents; and a second latching circuit coupled to the output of said first latching circuit, wherein said first latch circuit converts the first and second currents into the voltage level representing the logical value of the content of the cell and said second latching circuit maintains the logic value until the next read operation is performed on the cell.
29. A memory circuit comprising: a memory cell; an input circuit connected to said memory cell via first and second bit lines, said input circuit inputting data to be written into said memory cell; a current generating circuit connected to said input circuit, said current generating circuit generating first and second currents in response to the input data and applying the first and second currents onto the bit lines during a write operation, said first and second currents representing a value of the input data; a current sensing circuit connected to the first and second bit lines, said current sensing circuit respectively sensing third and fourth currents from the first and second bit lines during a read operation; and a conversion circuit coupled to said third and fourth currents, said conversion circuit converting the third and fourth currents into a voltage level representing a logical value of a content of the cell.
30. A processor system comprising: a processor; a memory circuit connected to said processor, said memory circuit comprising a differential write driver for a static memory circuit, said write driver comprising: an input circuit connected to a memory cell via first and second bit lines, said input circuit having first and second inputs for inputting data to be written into said memory cell; and a current generating circuit connected to said first and second inputs, said current generating circuit generating first and second currents in response to the input data and applying the first and second currents onto the bit lines, said first and second currents representing a value of the input data.
31. The system of claim 30 , wherein said write driver further comprises a biasing circuit coupled to said bit lines, said biasing circuit biasing the bit lines to a predetermined voltage level when a write operation is not being performed.
32. The system of claim 31 , wherein the predetermined voltage is smaller than a first voltage used to power the driver, but more than half of the first voltage.
33. The system of claim 31 , wherein the predetermined voltage is approximately fifty-five percent of the first voltage.
34. The system of claim 30 , wherein said write driver further comprises a biasing circuit coupled to said bit lines, said biasing circuit biasing the bit lines to a predetermined voltage level when a read operation or a write operation is not being performed.
35. The system of claim 34 , wherein the predetermined voltage is smaller than a first voltage used to power the driver, but more than half of the first voltage.
36. The system of claim 34 , wherein the predetermined voltage is approximately fifty-five percent of the first voltage.
37. A processor system comprising: a processor; a memory circuit connected to said processor, said memory circuit comprising a differential write driver for a static memory circuit, said write driver comprising: an input circuit connected to a memory cell via first and second bit lines, said input circuit having first and second inputs for inputting data to be written into said memory cell; and a current generating circuit connected to said first and second inputs, said current generating circuit generating first and second currents in response to the input data and applying the first and second currents onto the bit lines, said first and second currents representing a value of the input data or a tri-state condition, wherein said current generating circuit comprises: a first adjustable resistive element connected to a first voltage, a resistance of said first adjustable resistive element being controllable by a first control signal; a second adjustable resistive element connected to a second voltage, a resistance of said second adjustable resistive element being controllable by a second control signal; a first switch for switching in the resistance of the first adjustable resistive element in response to a third control signal; and a second switch for switching in the resistance of the second adjustable resistive element in response to a fourth control signal, wherein said first voltage is applied to said first adjustable resistive element and said second voltage is applied to said second adjustable resistive element when said third and fourth control signals are received.
38. The system of claim 37 , wherein the fourth control signal is a complement of the third control signal.
39. The system of claim 37 , wherein said third control signal is an enable signal and the fourth control signal is a complement of the enable signal.
40. The system of claim 37 , wherein said write driver further comprises a current loop generating circuit for generating the first and second control signals based on a reference voltage and a resistance of said current loop generating circuit.
41. The system of claim 30 , wherein said input circuit further comprises an input logic circuit for inputting the data and first and second control signals, wherein said first and second control signals are used to determine if a read or write operation is in progress.
42. A processor system comprising: a processor; a memory circuit connected to said processors said memory circuit comprising a differential write driver for a static memory circuit, said write driver comprising: an input circuit connected to a memory cell via first and second bit lines, said input circuit having first and second inputs for inputting data to be written into said memory cell; a current generating circuit connected to said first and second inputs, said current generating circuit generating first and second currents in response to the input data and applying the first and second currents onto the bit lines, said first and second currents representing a value of the input data or a tri-state condition; and a biasing circuit comprising: a first resistive element coupled between a first voltage and the first bit line; a second resistive element coupled between a second voltage and the second bit line; and a third resistive element coupled between the first and second bit lines, wherein said resistive elements are controlled to produce a predetermined voltage level on said bit lines when a write operation is not being performed.
43. The system of claim 42 , wherein said biasing circuit further comprises a bit line reference and said bit line reference is used to generate said predetermined voltage.
44. A processor system, comprising: a processor; and a memory circuit connected to said processor, said memory circuit comprising a current sensing receiver circuit for a static memory device comprising: a current sensing circuit connected to first and second bit lines, said current sensing circuit respectively sensing first and second currents from said first and second bit lines, said bit lines being connected to a memory cell of the device; and a conversion circuit coupled to said first and second currents, said conversion circuit converting the first and second currents into a voltage level representing a logical value of a content of the cell and latching the logical value until the next read operation is performed on the cell.
45. The system of claim 44 wherein said conversion circuit comprises a flip-flop circuit.
46. The system of claim 45 wherein the flip-flop circuit latches the logical value until the next read operation is performed on the cell.
47. The system of claim 44 wherein said conversion circuit comprises: a first latching circuit coupled to said first and second currents; and a second latching circuit coupled to the output of said first latching circuit, wherein said first latch circuit converts the first and second currents into the voltage level representing the logical value of the content of the cell and said second latching circuit maintains the logic value until the next read operation is performed on the cell.
48. A memory circuit comprising: a static memory cell connected to first and second bit lines; an input circuit, said input circuit having first and second inputs, said inputs corresponding inputting data to be written into a memory cell; and a current generating circuit connected to said input circuit, said current generating circuit generating first and second currents in response to the input data and applying the first and second currents to the memory cell through the bit lines, said first and second currents representing a value of the input data.
49. The memory circuit of claim 48 , further comprising a biasing circuit coupled to said bit lines, said biasing circuit biasing the bit lines to a predetermined voltage level when a write operation is not being performed.
50. The memory circuit of claim 48 , further comprising a biasing circuit coupled to said bit lines, said biasing circuit biasing the bit lines to a predetermined voltage level when a read operation or a write operation is not being performed.
51. The memory circuit of claim 50 , wherein the predetermined voltage is smaller than a first voltage used to power the driver, but more than half of the first voltage.
52. A memory circuit comprising: a static memory cell connected to first and second bit lines; an input circuit, said input circuit having first and second inputs, said inputs corresponding inputting data to be written into a memory cell; and a current generating circuit connected to said input circuit, said current generating circuit generating first and second currents in response to the input data and applying the first and second currents onto the bit lines, said first and second currents representing a value of the input data or a tri-state condition, wherein said current generating circuit comprises: a first adjustable resistive element connected to a first voltage, a resistance of said first adjustable resistive element being controllable by a first control signal; a second adjustable resistive element connected to a second voltage, a resistance of said second adjustable resistive element being controllable by a second control signal; a first switch for switching in the resistance of the first adjustable resistive element in response to a third control signal; and a second switch for switching in the resistance of the second adjustable resistive element in response to a fourth control signal, wherein said first voltage is applied to said first adjustable resistive element and said second voltage is applied to said second adjustable resistive element when said third and fourth control signals are received.
53. The memory circuit of claim 52 , further comprising a current loop generating circuit for generating the first and second control signals based on a reference voltage and a resistance of said current loop generating circuit.
54. The memory circuit of claim 48 , wherein said input circuit further comprises an input logic circuit for inputting the data and first and second control signals, wherein said first and second control signals are used to determine if a read or write operation is in progress.
55. A memory circuit comprising: a static memory cell connected to first and second bit lines; an input circuit, said input circuit having first and second inputs, said inputs corresponding inputting data to be written into a memory cell; a current generating circuit connected to said input circuit, said current generating circuit generating first and second currents in response to the input data and applying the first and second currents onto the bit lines, said first and second currents representing a value of the input data or a tri-state condition; and a biasing circuit comprising: a first resistive element coupled between a first voltage and the first bit line; a second resistive element coupled between a second voltage and the second bit line; and a third resistive element coupled between the first and second bit lines, wherein said resistive elements are controlled to produce a predetermined voltage level on said bit lines when a write operation is not being performed.
56. The memory circuit of claim 48 , wherein the memory cell is a static random access memory cell.
57. The memory circuit of claim 48 , wherein the memory cell is a content addressable memory cell.
58. A memory circuit comprising: a static memory cell connected to first and second bit lines; a current sensing circuit connected to said first and second bit lines, said current sensing circuit respectively sensing first and second currents from said first and second bit lines; and a conversion circuit coupled to said first and second currents, said conversion circuit converting the first and second currents into a voltage level representing a logical value of a content of said cell and maintaining the logic value until the next read operation is performed on the cell.
59. The memory circuit of claim 58 , wherein said conversion circuit comprises a flip-flop circuit that latches the logical value until the next read operation is performed on the cell.
60. The memory circuit of claim 58 , wherein said conversion circuit comprises: a first latching circuit coupled to said first and second currents; and a second latching circuit coupled to the output of said first latching circuit, wherein said first latch circuit converts the first and second currents into the voltage level representing the logical value of the content of the cell and said second latching circuit maintains the logic value until the next read operation is performed on the cell.
61. A network router comprising: a processor; and a content addressable memory device connected to said processor, said content addressable memory comprising: a content addressable memory cell; an input circuit connected to input data to be written into said memory cell; a current generating circuit connected to said input circuit, said current generating circuit generating first and second currents in response to the input data and applying the first and second currents onto the bit lines during a write operation, said first and second currents representing a value of the input data; a current sensing circuit connected to the first and second bit lines, said current sensing circuit respectively sensing third and fourth currents from the first and second bit lines during a read operation; and a conversion circuit coupled to said third and fourth currents, said conversion circuit converting the third and fourth currents into a voltage level representing a logical value of a content of the cell.
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July 3, 2002
January 13, 2004
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