Patentable/Patents/US-6678948
US-6678948

Method for connecting electronic components to a substrate, and a method for checking such a connection

PublishedJanuary 20, 2004
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A method for connecting an electronic components to a carrier substrate is described. At least one pad of the component is connected electrically conductively to at least one pad on an upper surface of the carrier substrate. A solder bump is deposited on at least one of the pads to be connected, the component is alignedly mated with the carrier substrate, and the at least one solder bump is soldered in order to wet the contact surfaces.It is provided that during the soldering, the at least one solder bump is deformed within the contacting plane in such a way as to achieve a degree of deformation that permits the two-dimensional analysis of said degree of deformation by a radiograph of the interconnection site.

Patent Claims
14 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A method for connecting at least one electronic component to a carrier substrate, comprising the steps of: electrically conductively connecting at least one pad of the at least one electronic component to at least one pad of the carrier substrate; depositing a solder bump on one of the at least one pad of the at least one electronic component and the at least one pad of the carrier substrate; alignedly mating the at least one electronic component with the carrier substrate; soldering the solder bump to wet contact surfaces of the at least one electronic component and the carrier substrate; deforming the solder bump within a contacting plane during soldering so that a degree of deformation is achieved that permits an analysis of the degree of deformation by a radiograph of the contact surfaces; and evaluating a continuous intensity distribution of the radiograph along a line.

2

2. The method according to claim 1 , wherein: during the step of soldering the solder bump is distributed so that a thickness of a soldering material decreases continuously toward a margin.

3

3. The method according to claim 1 , further comprising the step of: determining the degree of deformation of the solder bump by a solder stop mask, the solder stop mask encompassing the at least one pad of the carrier substrate, the solder bump being fitted into the at least one pad of the carrier substrate.

4

4. The method according to claim 1 , further comprising the step of: determining the degree of deformation of the solder bump by a size ratio of a first diameter of masking openings in a solder stop mask to a second diameter of the solder bump.

5

5. The method according to claim 1 , further comprising the step of: intentionally regionally wetting printed circuit traces to cause the deformation of the solder bump, the printed circuit traces including the at least one pad of the carrier substrate.

6

6. The method according to claim 1 , further comprising the step of: intentionally wetting edge surfaces of the at least one pad of the carrier substrate to cause the deformation of the solder bump.

7

7. The method according to claim 1 , wherein: the deformation of the solder bump is effected by a deliberate wetting of the at least one pad of the carrier substrate, the at least one pad of the carrier substrate deviating from a circular shape.

8

8. The method according to claim 1 , further comprising the step of: using a flip-chip technique to form the connection between the at least one pad of the at least one electronic component and the at least one pad of the carrier substrate.

9

9. The method according to claim 1 , further comprising the step of: using a ball grid array technique to form the connection between the at least one pad of the at least one electronic component and the carrier substrate.

10

10. The method according to claim 1 , wherein the evaluating step includes the substep of identifying abrupt transitions.

11

11. The method according to claim 1 , wherein the evaluating step includes the substep of determining wetting of vertical sidewalls of the at least one pad.

12

12. A method for examining a connection between an electronic component and a carrier substrate, pads of the electronic component being connected to assigned pads of the carrier substrate via at least one solder bump, comprising the steps of: after connection of the electronic component to the carrier substrate, exposing a bonding arrangement to x-rays directed perpendicularly to a contacting plane; making a radiograph on a side of the bonding arrangement facing away from an x-ray source; and analyzing an intensity variation of the x-rays in a transitional region from a solder bump to a region surrounding the solder bump, the solder bump being deformed during soldering so that one of a continuous transition of the intensity variation from a minimum intensity to a maximum intensity and a set deformation of the solder bump is measurable when proper wetting of the assigned pads has taken place.

13

13. The method according to claim 12 , further comprising the step of: preparing and analyzing a two-dimensional radiograph of the bonding arrangement.

14

14. The method according to claim 12 , further comprising the step of: preparing and analyzing a three-dimensional radiograph of the bonding arrangement in a region of a layer, the layer lying in a plane with at least one pad of the carrier substrate.

Classification Codes (CPC)

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Patent Metadata

Filing Date

December 11, 2000

Publication Date

January 20, 2004

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