A method of forming a shallow trench isolation of a semiconductor device, includes providing a semiconductor substrate including field and active regions; forming a first insulating layer and a mask layer on the active region that expose the field region; etching the exposed field region to form a shallow trench; etching a portion of the mask layer to recess the mask layer a predetermined distance from an edge of the trench; forming a second insulating layer in the trench, the second insulating layer having a step higher than the active region; forming a liner layer as covering the mask layer and the second insulating layer; forming a third insulating layer as covering the liner layer and filling the trench; etching the mask, liner and third insulating layers to provide a planarized surface; removing the remaining mask layer; and removing the remaining first insulating layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method of forming a shallow trench isolation of a semiconductor device, comprising: providing a semiconductor substrate including a field region and an active region; forming a first insulating layer and a mask layer on the active region that expose the field region of the substrate; etching the exposed field region of the substrate to form a shallow trench; wet-etching a portion of the mask layer to recess the mask layer a predetermined distance from an edge of the shallow trench using a pull-back process; forming a second insulating layer in the shallow trench, the second insulating layer having a step higher than the active region; forming a liner layer as covering the mask layer and the second insulating layer within the shallow trench; forming a third insulating layer as covering the liner layer and filling the shallow trench; etching the mask layer, the liner layer and the third insulating layer to provide a planarized surface; removing a remaining portion of the mask layer; and removing a remaining portion of the first insulating layer.
2. The method of claim 1 , wherein the mask layer and the liner layer comprise nitride layers.
3. The method of claim 1 , wherein the first insulating layer is a pad oxide layer, and the second insulating layer is a buffer oxide layer.
4. The method of claim 1 , wherein the second insulating layer has a thickness of 100 to 700 .
5. The method of claim 4 , wherein the second insulating layer is a thermal oxidation layer formed by a thermal oxidation process.
6. The method of claim 4 , wherein the second insulating layer is a CVD oxide layer.
7. The method of claim 1 , wherein the third insulating layer is a high density plasma (HDP) oxide layer or an undoped silicon glass (USG) layer.
8. The method of claim 1 , wherein said forming a first insulating layer and a mask layer further comprises forming an anti-reflection layer on the mask layer that also exposes the field region of the substrate.
9. The method of claim 8 , wherein the anti-reflection layer prevents reduction of a thickness of the mask layer during said etching a portion of the mask layer.
10. A method of forming a shallow trench isolation of a semiconductor device, comprising: providing a semiconductor substrate including a field region and an active region; forming a first insulating layer and a mask layer on the substrate that expose the field region of the substrate; etching the exposed field region of the substrate to form a shallow trench; wet-etching a portion of the mask layer to recess the mask layer a predetermined distance from an edge of the shallow trench using a pull-back process; forming a second insulating layer in the shallow trench, the second insulating layer having a step higher than the active region; forming a liner layer as covering the mask layer and the second insulating layer within the shallow trench; forming a third insulating layer as covering the liner layer and filling the shallow trench; etching the mask layer, the liner layer and the third insulating layer to provide a planarized surface; removing a remaining portion of the mask layer; removing a remaining portion of the first insulating layer; cleaning the substrate; and forming a gate oxide layer on the active region of the substrate.
11. The method of claim 10 , wherein the mask layer and the liner layer comprise nitride layers.
12. The method of claim 10 , wherein the first insulating layer is a pad oxide layer, and the second insulating layer is a buffer oxide layer.
13. The method of claim 10 , wherein the second insulating layer has a thickness of 100 to 700 .
14. The method of claim 13 , wherein the second insulating layer is a thermal oxidation layer formed by a thermal oxidation process.
15. The method of claim 13 , wherein the second insulating layer is a CVD oxide layer.
16. A method of forming a semiconductor device, comprising: providing a semiconductor substrate including a field region and first and second active regions; forming a first insulating layer and a mask layer on the substrate to expose the field region of the substrate; etching the exposed field region of the substrate to form a shallow trench; wet-etching a portion of the mask layer to recess the mask layer a predetermined distance from an edge of the shallow trench using a pull-back process; forming a second insulating layer in the shallow trench, the second insulating layer having a step higher than the first and second active regions; forming a liner layer as covering the mask layer and the second insulating layer within the shallow trench; forming a third insulating layer as covering the liner layer and filling the shallow trench; etching the mask layer, the liner layer and the third insulating layer to provided a planarized surface; removing a remaining portion of the mask layer; removing a remaining portion of the first insulating layer; cleaning the substrate; forming a first gate oxide layer over an entire surface of the substrate; etching the first gate oxide layer so that the first gate oxide layer remains on the first active region of the substrate; and forming a second gate oxide layer on the second active region of the substrate.
17. The method of claim 16 , wherein the mask layer and the liner layer comprise nitride layers.
18. The method of claim 16 , wherein the first insulating layer is a pad oxide layer, and the second insulating layer is a buffer oxide layer.
19. The method of claim 16 , wherein the second insulating layer has a thickness of 100 to 700 .
20. The method of claim 19 , wherein the second insulating layer is a CVD oxide layer or a thermal oxide layer.
21. The method of claim 16 , wherein the third insulating layer is a high density plasma (HDP) oxide layer or an undoped silicon glass (USG) layer.
22. The method of claim 16 , wherein the first and second gate oxide layers are formed by a thermal oxidation process.
23. The method of claim 16 , wherein the first gate oxide layer is thicker than the second gate oxide layer.
24. The method of claim 23 , wherein the first gate oxide layer has a thickness of 100 to 700 , and the second gate oxide layer has a thickness of less than 80 .
25. The method of claim 16 , wherein the first gate oxide layer is thinner than the second gate oxide layer.
26. The method of claim 25 , wherein the first gate oxide layer has a thickness of less than 80 , and the second gate oxide layer has a thickness of 100 to 700 .
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 19, 2002
January 27, 2004
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