An apparatus and method for issue grouping of instructions in a VLIW processor is disclosed. There can be one, two, or three issue groups (but no greater than three issue groups) in each VLIW packet. In one embodiment, a template in the VLIW packet comprises two issue group end markers where each issue group end marker comprises three bits. The three bits in the first issue group end marker identifies the instruction which is the last instruction in the first issue group. Likewise, the three bits in the second issue group end marker identifies the instruction which is the last instruction in the second issue group. Any instructions in the VLIW packet falling outside the two expressly defined first and second issue groups are placed in a third issue group. As such, three issue groups can be identified by use of the two issue group end markers. In one embodiment, the template of the VLIW packet includes a chaining bit. The chaining bit is used to “chain” instructions appearing after the last instruction of the last issue group of a first VLIW packet to the instructions in the first issue group of a second VLIW packet. In one embodiment, a mask generation logic along with other logic blocks are utilized to generate an appropriate mask. The generated mask is used to pass through instructions in a VLIW packet which belong to a same issue group for execution in a same clock cycle.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A processor comprising: a first plurality of instructions in a first packet of instructions in said processor; a second plurality of instructions in a second packet of instructions in said processor; a first packet template, said first packet template including a chaining bit; said chaining bit indicating that a third plurality of instructions in said first packet and a fourth plurality of instructions in said second packet are to be placed in a combined issue group; wherein said first packet template identifies each of said third plurality of instructions that are to be placed in said combined issue group, wherein a second packet template identifies each of said fourth plurality of instructions in said second packet that are to be placed in said combined issue group.
2. The processor of claim 1 wherein said first plurality of instructions is divided into said third plurality and a fifth plurality of instructions, wherein said fifth plurality of instructions is divided into a plurality of first packet issue groups.
3. The processor of claim 2 wherein said plurality of first packet issue groups comprises at most three first packet issue groups.
4. The processor of claim 1 wherein said second plurality of instructions is divided into said fourth plurality and a sixth plurality of instructions, wherein said sixth plurality of instructions is divided into a plurality of second packet issue groups.
5. The processor of claim 4 wherein said plurality of second packet issue groups comprises at most three second packet issue groups.
6. The processor of claim 1 said first packet template includes a plurality of first packet end markers, said plurality of first packet end markers identifying at most three first packet issue groups.
7. The processor of claim 1 wherein said second packet template includes a plurality of second packet end markers, said plurality of said packet end markers identifying at most three second packet issue groups.
8. The processor of claim 1 wherein each of said first and second pluralities is equal to seven.
9. The processor of claim 1 wherein each of said first and second packets comprises at least 128 bits and each of said first plurality of instructions and said second plurality of instructions comprises at least 16 bits.
10. The processor of claim 6 wherein each of said plurality of first packet end markers comprises at most three bits.
11. The processor of claim 7 wherein each of said plurality of second packet end markers comprises at most three bits.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 28, 2002
January 27, 2004
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