There is a need for adjustable capacitors for use in LC or RC matching networks in micro-circuits. This has been achieved by forming a set of individual capacitors that share a common bottom electrode. The areas of the top electrodes of these individual capacitors are chosen to be in an integral ratio to one another so that they can be combined to produce any capacitance within a range of unit values. For example, if four capacitors whose areas are in the ratio of 5:2:1:1, are provided, then any capacitance in a range of from 1 to 9 can be generated, depending on how the top electrodes are connected. Such connections can be hard-wired within the final wiring level to provide a factory adjustable capacitor or they can be connected through field programmable devices to produce a field programmable capacitor. A process for manufacturing the device is also described.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A process for forming an adjustable capacitor, comprising: providing a silicon wafer having a topmost layer on which are contact pads connected to a circuit contained in said wafer; depositing a base dielectric layer on said topmost layer, including said contact pads; on said base dielectric layer, depositing an etch stop layer, selected from the group consisting of silicon nitride and silicon carbide, to a thickness between about 20 and 500 microns; depositing a support dielectric layer on said etch stop layer; etching a via hole through said support dielectric layer, said etch stop layer, and said base dielectric layer, thereby exposing said contact pad; depositing a barrier layer in said via hole, then overfilling said via hole with tungsten and then planarizing so as to remove all tungsten not inside said via; etching three trenches that extend through said support dielectric layer as far as said etch stop layer; depositing a first layer of metal on said support dielectric layer, including inside said trenches, and then patterning said first metal layer to form a common capacitor electrode that contacts said tungsten-filled via hole; depositing a layer of high dielectric constant material on said common capacitor electrode and then patterning said high dielectric constant layer whereby it fully overlaps said common capacitor electrode; depositing a second layer of metal on said high dielectric constant layer and then patterning said second metal layer to form four unconnected top electrodes, all of whom are overlapped by said common electrode, said top electrodes having, relative to one another, areas in the ratio 5:2:1:1; depositing a top dielectric layer on said top electrodes and said high dielectric constant layer; etching four via holes through said top dielectric layer whereby a contact area is exposed for each of said top electrodes; depositing a barrier layer in said via holes, then overfilling said via holes with tungsten and then planarizing so as to remove all tungsten not inside said via holes; and then depositing and patterning a third metal layer so as to provide permanent connections between said top electrodes, thereby giving said adjustable capacitor a specific capacitance value.
2. The process described in claim 1 wherein said base dielectric layer is selected from the group consisting of silicon oxide, TEOS, black diamond, and all dielectrics having a dielectric constant less than about 5 and said base dielectric layer is deposited to a thickness between about 200 and 5,000 Angstroms.
3. The process described in claim 1 wherein said support dielectric layer is selected from the group consisting of silicon oxide, black diamond, and all dielectrics having a dielectric constant less than about 5 and said support dielectric layer is deposited to a thickness between about 200 and 5,000 Angstroms.
4. The process described in claim 1 wherein said metal layers are selected from the group consisting of Al, Ti, TiN, and all metals whose resistivity is less than about 5 microhm-cm, and are deposited to a thickness between about 200 and 5,000 Angstroms.
5. The process described in claim 1 wherein said layer of high dielectric constant material is selected from the group consisting of silicon nitride, tantalum oxide, aluminum oxide, and hafnium oxide and is deposited to a thickness between about 20 and 500 Angstroms.
6. The process described in claim 1 wherein each trench has a width between about 0.1 and 0.8 microns and said trenches are separated from one another by between about 0.1 and 0.8 microns.
7. A process for forming a field programmable capacitor, comprising: providing a silicon wafer having a topmost layer on which are contact pads connected to a circuit contained in said wafer; depositing a base dielectric layer on said topmost layer, including said contact pads; on said base dielectric layer, depositing an etch stop layer, selected from the group consisting of silicon nitride and silicon carbide, to a thickness between about 20 and 500 microns; depositing a support dielectric layer on said etch stop layer; etching a via hole through said support dielectric layer, said etch stop layer, and said base dielectric layer, thereby exposing said contact pad; depositing a barrier layer in said via hole, then overfilling said via hole with tungsten and then planarizing so as to remove all tungsten not inside said via; etching three trenches that extend through said support dielectric layer as far as said etch stop layer; depositing a first layer of metal on said support dielectric layer, including inside said trenches, and then patterning said first metal layer to form a common capacitor electrode that contacts said tungsten-filled via hole; depositing a layer of high dielectric constant material on said common capacitor electrode and then patterning said high dielectric constant layer whereby it fully overlaps said common capacitor electrode; depositing a second layer of metal on said high dielectric constant layer and then patterning said second metal layer to form four unconnected top electrodes, all of whom are overlapped by said common electrode, said top electrodes having, relative to one another, areas in the ratio 5:2:1:1; depositing a top dielectric layer on said top electrodes and said high dielectric constant layer; etching four via holes through said top dielectric layer whereby a contact area is exposed for each of said top electrodes; depositing a barrier layer in said via holes, then overfilling said via holes with tungsten and then planarizing so as to remove all tungsten not inside said via holes; and then depositing and patterning a third metal layer to form a contact wire for each of said filled via holes; and connecting said contacting wires to each other through field programmable devices, thereby forming said field programmable capacitor.
8. The process described in claim 7 wherein said field programmable devices are selected from the group consisting of fusible links, anti-fuses, pass transistors, resistors, and capacitors.
9. The process described in claim 7 wherein said base dielectric layer is selected from the group consisting of silicon oxide, black diamond, and all dielectrics having a dielectric constant less than about 5 and said base dielectric layer is deposited to a thickness between about 200 and 5,000 Angstroms.
10. The process described in claim 7 wherein said support dielectric layer is selected from the group consisting of silicon oxide, black diamond, and all dielectrics having a dielectric constant less than about 5 and said support dielectric layer is deposited to a thickness between about 200 and 5,000 Angstroms.
11. The process described in claim 7 wherein said metal layers are selected from the group consisting of Al, Ti, TiN, and all metals whose resistivity is less than about 5 microhm-cm, and are deposited to a thickness between about 200 and 5,000 Angstroms.
12. The process described in claim 7 wherein said layer of high dielectric constant material is selected from the group consisting of silicon nitride, tantalum oxide, aluminum oxide, and hafnium oxide and is deposited to a thickness between about 20 and 500 Angstroms.
13. The process described in claim 7 wherein each trench has a width between about 0.1 and 0.8 microns and said trenches are separated from one another by between about 0.1 and 0.8 microns.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 25, 2002
February 10, 2004
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