A semiconductor device with adjustable number of pages and page depth is disclosed. The semiconductor device includes multiple memory cell array blocks, a page control circuit for generating a control signal which varies the number of pages and the page depth in response to a page control signal, and a sense amplifying and write driving circuit. The page control circuit controls a row address and a column address to generate the control signal, that is, to vary the number of pages and the page depth. The sense amplifying and write driving circuit senses, amplifies and outputs data from a memory cell array block, and writes data into a memory cell array block in response to the control signal. The page control circuit includes an address buffer, a block controller and a control signal generator. The address buffer buffers the most significant bit (MSB) of the row address and outputs the buffered result, or ignores the MSB depending on the page control signal. The block controller generates a block select signal in response to the MSB and a bit next to the MSB of the row address, and the control signal generator, depending on the page control signal, selects between the MSB of the column address and the block select signal as the control signal.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device in which a page length and a page depth respectively are 2 NR and 2 NC where NR is the number of bits in a row address and NC is the number of bits in a column address, the semiconductor device comprising: a plurality of memory cell array blocks; and a page control circuit which, depending on a page control signal, controls the number of bits in the row address used and the number of bits in the column address used to generate a control signal which varies the page length and page depth.
2. The semiconductor device of claim 1 , wherein the page control circuit comprises: an address buffer that generates a block address signal in response to the page control signal; a plurality of block controllers that generate a block select signal in response to the block address signal from the address buffer; and a plurality of control signal generators that output one of the block select signals and a most significant bit of the column address as the control signal in response to the page control signal.
3. The semiconductor device of claim 1 , wherein the page control signal is fixed to the semiconductor device, so that a set of the page length and the page depth are permanently selected from among a plurality of sets of the number of pages and the page depth that are available in the semiconductor device.
4. The semiconductor device of claim 3 , wherein the page control signal is fixed by a wire bonding option in packaging the semiconductor device.
5. The semiconductor device of claim 1 , wherein the page control signal is applied to the semiconductor device from an external control circuit.
6. The semiconductor device of claim 1 , further comprising: a plurality of sense amplifiers; and a plurality of write drivers; wherein the control signal selects the sense amplifiers and the write drivers.
7. The semiconductor device of claim 1 , wherein: in a first mode, one of the memory cell array blocks is activated by two upper most significant bits of the row address transmitted to the block controller; and in a second mode, the most significant bit of the row address is ignored, and two blocks, discriminated by a most significant bit of a column address, are activated.
8. A semiconductor device in which a page length and a page depth respectively are 2 NR and 2 NC where NR is the number of bits in a row address and NC is the number of bits in a column address, the semiconductor device comprising: a plurality of memory cell array blocks; and a page control circuit which, depending on a page control signal, controls the number of bits in the row address used to generate a control signal which varies the page length and page depth.
9. A semiconductor device in which a page length and a page depth respectively are 2 NR and 2 NC where NR is the number of bits in a row address and NC is the number of bits in a column address, the semiconductor device comprising: a plurality of memory cell array blocks; and a page control circuit which, depending on a first control signal, controls the number of bits in the row address and the number of bits in the column address used to generate a second control signal which varies the page length and page depth.
10. A semiconductor device in which a page length and a page depth respectively are 2 NR and 2 NC where NR is the number of bits in a row address and NC is the number of bits in a column address, the semiconductor device comprising: a plurality of memory cell array blocks; and a page control circuit which, depending on a first control signal, determines whether a bit in the column address will be used to generate a second control signal which varies the page length and page depth.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 14, 1999
February 17, 2004
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