Disclosed in a power semiconductor module which includes a stack of carrier substrates, disposed one above the other in multiple layers and provided with at least one conductor track on at least one main surface, in which at least one electronic semiconductor component is disposed between two adjacent carrier substrates of the stack and is contacted electrically and heat-conductively to at least one conductor track of a carrier substrate disposed in the stack above the semiconductor component and to at least one further conductor track of a carrier substrate disposed in the stack below the semiconductor component. To both improve heat output and provide a compact design, the two outer carrier substrates of the stack are embodied as one upper and one lower housing wall of a closed housing part surrounding the at least one semiconductor component, and the interstices between the stacked carrier substrates are tightly closed by an encompassing wall secured to the carrier substrates.
Legal claims defining the scope of protection, as filed with the USPTO.
1. In a power semiconductor module, including a stack of carrier substrates ( 1 , 2 , 3 ), disposed one above the other in multiple layers, which are provided on at least one main surface with at least one conductor track ( 31 - 36 ), at least one electronic semiconductor component ( 40 - 47 ) being disposed between two adjacent carrier substrates of the stack and being contacted electrically and heat-conductively to at least one conductor track ( 31 - 36 ) of a carrier substrate disposed in the stack above the semiconductor component and to at least one further conductor track ( 31 - 36 ) of a carrier substrate disposed in the stack below the semiconductor component, the improvement wherein the two outer carrier substrates ( 1 , 3 ) of the stack form one upper and one lower housing wall of a closed housing part surrounding the at least one semiconductor component ( 40 - 47 ), the heat generated by the semiconductor component being dissipated at least in part to the upper and lower housing walls formed by the outer carrier substrates ( 1 , 3 ) and from there being radiated to the surroundings of the housing part; and that the interstices ( 4 , 5 ) between the stacked carrier substrates are tightly closed by an encompassing wall ( 70 , 80 , 100 ) secured to the carrier substrates.
2. The power semiconductor module of claim 1 , wherein the housing part formed by the upper and lower housing wall ( 1 , 3 ) and the encompassing wall ( 70 , 80 , 100 ) is a hermetically sealed housing part.
3. The power semiconductor module of claim 1 , wherein the electrically contacting of the at least one semiconductor component ( 40 - 47 ) to the at least one conductor track ( 31 - 36 ) of the carrier substrate disposed above the semiconductor component and to the at least one further conductor track ( 31 - 36 ) of the carrier substrate disposed below the semiconductor component is effected by soldering.
4. The power semiconductor module of claim 1 , wherein the interstices ( 4 , 5 ) between the stacked carrier substrates ( 1 , 2 , 3 ) are completely filled by a flowable, curable and heat-conducting medium ( 101 ).
5. The power semiconductor module of claim 4 , wherein the flowable, curable and heat-conducting medium is applied to the carrier substrate face ends ( 15 , 16 , 17 ) extending perpendicular to the main surfaces of the carrier substrates ( 1 - 3 ) in such a way that the flowable, curable medium ( 101 ) simultaneously forms the encompassing wall ( 100 ).
6. The power semiconductor module of claim 4 , wherein the flowable, curable and heat-conducting medium ( 101 ) is a capillary flowable adhesive.
7. The power semiconductor module of claim 4 , wherein the flowable, curable and heat-conducting medium ( 101 ) is an injection molding composition.
8. The power semiconductor module of claim 1 , wherein contact elements ( 51 - 56 ) are provided, which are each electrically contacted to a respective conductor track ( 31 - 36 ) disposed on a carrier substrate ( 1 - 3 ) and are extended laterally out of the interstices ( 4 , 5 ) between the carrier substrates ( 1 - 3 ) and are extended through the encompassing wall ( 70 , 100 ) to the outside out of the housing part.
9. The power semiconductor module of claim 8 , wherein insulating leadthroughs ( 59 ) for the contact elements ( 51 - 56 ) are provided in the encompassing wall ( 70 ).
10. The power semiconductor module of claim 9 , wherein the insulating leadthroughs ( 59 ) are glass leadthroughs, which are each introduced into a recess of the encompassing wall ( 70 ) and surround one contact element ( 51 - 56 ) in hermetically sealed fashion.
11. The power semiconductor module of claim 10 , wherein the encompassing wall ( 70 ) is affixed at least in part to the carrier substrate face ends ( 15 , 16 , 17 ) extending perpendicular to the main surface of the carrier substrates ( 1 - 3 ).
12. The power semiconductor module of claim 1 , wherein the encompassing wall is formed by at least one closed encompassing frame ( 80 ), which is placed between an upper and a lower carrier substrate ( 1 , 2 , 3 ) in such a way that at least the at least one semiconductor component ( 40 - 47 ) is completely surrounded by the frame ( 80 ), and the frame is tightly joined to the upper carrier substrate and the lower carrier substrate.
13. The power semiconductor module of claim 12 , wherein the frame ( 80 ) is a metal frame and is soldered over a large surface area to an encompassing conductor track ( 38 ) of the upper carrier substrate and to an encompassing conductor track ( 39 ) of the lower carrier substrate.
14. The power semiconductor module of claim 12 , wherein the electrical terminals of the semiconductor components ( 40 - 47 ) are extended to the outside via via-holes ( 81 - 86 ) in the carrier substrates ( 1 , 2 , 3 ) and on the outside of the outer carrier substrates ( 1 , 3 ) are electrically connected to contact elements ( 51 - 56 ).
15. The power semiconductor module of claim 12 , wherein in the stack, at least one carrier substrate ( 2 ) is disposed with an elastically resilient layer ( 90 ) in such a way that the stack formed is elastically resiliently compressible in a direction perpendicular to the plane of the carrier substrates ( 1 , 2 , 3 ).
16. The power semiconductor module of claim 15 , wherein the elastically resilient layer ( 90 ) is fabricated from an elastically deformable plastic.
17. The power semiconductor module of claim 15 , wherein the elastically resilient layer ( 90 ) is formed by a plurality of spring elements disposed in the same plane.
18. The power semiconductor module of claim 5 , wherein the flowable, curable and heat-conducting medium ( 101 ) is a capillary flowable adhesive.
19. The power semiconductor module of claim 5 , wherein the flowable, curable and heat-conducting medium ( 101 ) is an injection molding composition.
20. The power semiconductor module of claim 13 , wherein the electrical terminals of the semiconductor components ( 40 - 47 ) are extended to the outside via via-holes ( 81 - 86 ) in the carrier substrates ( 1 , 2 , 3 ) and on the outside of the outer carrier substrates ( 1 , 3 ) are electrically connected to contact elements ( 51 - 56 ).
21. The power semiconductor module of claim 13 , wherein in the stack, at least one carrier substrate ( 2 ) is disposed with an elastically resilient layer ( 90 ) in such a way that the stack formed is elastically resiliently compressible in a direction perpendicular to the plane of the carrier substrates ( 1 , 2 , 3 ).
22. The power semiconductor module of claim 14 , wherein in the stack, at least one carrier substrate ( 2 ) is disposed with an elastically resilient layer ( 90 ) in such a way that the stack formed is elastically resiliently compressible in a direction perpendicular to the plane of the carrier substrates ( 1 , 2 , 3 ).
23. The power semiconductor module of claim 20 , wherein in the stack, at least one carrier substrate ( 2 ) is disposed with an elastically resilient layer ( 90 ) in such a way that the stack formed is elastically resiliently compressible in a direction perpendicular to the plane of the carrier substrates ( 1 , 2 , 3 ).
24. The power semiconductor module of claim 21 , wherein the elastically resilient layer ( 90 ) is fabricated from an elastically deformable plastic.
25. The power semiconductor module of claim 22 , wherein the elastically resilient layer ( 90 ) is fabricated from an elastically deformable plastic.
26. The power semiconductor module of claim 23 , wherein the elastically resilient layer ( 90 ) is fabricated from an elastically deformable plastic.
27. The power semiconductor module of claim 21 , wherein the elastically resilient layer ( 90 ) is formed by a plurality of spring elements disposed in the same plane.
28. The power semiconductor module of claim 22 , wherein the elastically resilient layer ( 90 ) is formed by a plurality of spring elements disposed in the same plane.
29. The power semiconductor module of claim 23 , wherein the elastically resilient layer ( 90 ) is formed by a plurality of spring elements disposed in the same plane.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 9, 2002
February 24, 2004
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