Patentable/Patents/US-6697381
US-6697381

Packet channel architecture

PublishedFebruary 24, 2004
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A packet data frame and system for transmitting and receiving the packet data frame. The packet data frame comprises a data signal and a header appended to the data signal. The header includes information corresponding to a length of the data signal used by the data communication system to transmit and receive the data signal in a contiguous sequence.

Patent Claims
19 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. A packet data frame comprising: a data signal; and a header appended to the data signal, the header comprising a start of packet synchronization code followed by a packet control word repeated twice and including an information corresponding to a length of the data signal, the information being used by a data communication system to transmit and receive the data signal in a contiguous sequence.

2

2. The data packet frame of claim 1 wherein the header comprises a 128-bit header.

3

3. The data packet frame of claim 1 wherein the header includes a packet control word comprising: the information corresponding to a length of the data signal; and a device identification code.

4

4. The data packet frame of claim 3 wherein the device identification code corresponds to a type of data contained in the data signal.

5

5. The data packet frame of claim 1 wherein the packet control word comprises a 32-bit word.

6

6. The data packet frame of claim 3 wherein the device identification code is contained in an upper 16-bits of a 32-bit packet control word and the information corresponding to the length of the data signal is contained in a lower 16-bits of the 32-bit packet control word.

7

7. The data packet frame of claim 1 wherein the header further comprises a start of packet synchronization code.

8

8. The packet data frame of claim 7 wherein the start of packet synchronization code comprises a 64-bit code.

9

9. The data packet frame of claim 1 wherein a start of packet synchronization code is appended to a beginning of the data packet frame.

10

10. The data packet frame of claim 1 wherein the data signal comprises a data packet including at least one data word.

11

11. The data packet frame of claim 1 wherein the information corresponding to the length of the data signal comprises a number of at least one data words contained in a data packet comprising the data signal.

12

12. The data packet frame of claim 1 wherein the data signal is associated with a peripheral computer interconnect ( PCI ) complaint sensor.

13

13. A system for transferring a data signal over a channel comprising: a first data transfer device adapted to append a header to a data signal and transmit the header and data signal over the channel, the header comprising a start up packet synchronization code followed by a packet control word repeated twice, and including an information corresponding to a length of the data signal, the information being used by the system to transmit and receive the data signal in a contiguous sequence; a second data transfer device coupled to the first data transfer device by the channel to receive the header and data signal, the second data transfer device being adapted to use the information corresponding to the length of the data signal to receive the data signal aligned in the same contiguous sequence as it was transmitted.

14

14. The system of claim 13 , wherein the first data transfer device comprises a data transmitter adapted to format the data signal into a data packet and transmit the data packet and header over the channel, the data packet being transmitted in a contiguous sequence.

15

15. The system of claim 14 wherein the data transmitter includes a mulltiplexer device adapted to format the data signal into the data packet, the multiplexer being further adapted to append the header to the data packet and forward the header and data packet to a transmitter assembly of the data transmitter for transmission over the channel.

16

16. The system of claim 13 wherein the second data transfer device comprises a data receiver adapted to receive the header and a data packet transmitted over the channel, the data packet being received in a sequence corresponding to the contiguous sequence it was transmitted in.

17

17. The system of claim 16 wherein the data receiver includes a demulitiplexer device adapted receive the data packet from a receiver portion of the data receiver and to use the information corresponding to the length of the data signal contained in the header to receive the data packet in the sequence corresponding to the contiguous sequence it was transmitted in.

18

18. The system of claim 13 wherein the channel comprises a common data link ( CDL ).

19

19. The system of claim 13 further comprising: a sensor coupled to the first data transfer device and adapted to provide the data signal to the system in the contiguous sequence; and a sensor device associated with the sensor, the sensor device coupled to the second data transfer device, the sensor device adapted to receive the data signal from the second data transfer device.

Classification Codes (CPC)

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Patent Metadata

Filing Date

March 9, 2000

Publication Date

February 24, 2004

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Cite as: Patentable. “Packet channel architecture” (US-6697381). https://patentable.app/patents/US-6697381

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