Provided is a method for forming a self aligned contact (SAC) of a semiconductor device that can minimize the loss of gate electrodes and hard mask. The method includes the steps of: providing a semiconductor substrate on which a plurality of conductive patterns are formed; forming a first insulation layer along the profile of the conductive patterns on the substrate; forming a second insulation layer on the substrate and simultaneously forming voids between the conductive patterns; forming a third insulation layer on the first insulation layer; and forming contact holes that expose the surface of the substrate between the conductive patterns by etching the third insulation layer and the second insulation layer covering the voids.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for forming a self aligned contact of a semiconductor device, comprising the steps of: providing a semiconductor substrate on which a plurality of conductive patterns are formed; forming a first insulation layer along the profile of the conductive patterns on the substrate; forming a second insulation layer on the substrate and simultaneously forming voids between the conductive patterns; forming a third insulation layer on the first insulation layer; and forming contact holes that expose the surface of the substrate between the conductive patterns by etching the third insulation layer and the second insulation layer covering the voids.
2. The method as recited in claim 1 , wherein the second insulation layer is formed in a thickness of 2,000 8,000 .
3. The method as recited in claim 1 , wherein the second insulation layer includes a PE-TEOS or an HDP oxide layer.
4. The method as recited in claim 1 , wherein the step of forming the second insulation layer is performed at 400 600 C. under a pressure of 1 10 Torr.
5. The method as recited in claim 4 , wherein in the step of forming the second insulation layer, reaction source contains SiH 4 whose flow rate is 100 500 SCCM, and N 2 O whose flow rate is 500 1,000 SCCM, and the RF power of 0.5 2.0 KW is used.
6. The method as recited in claim 3 , wherein the first insulation layer is formed with a silicon nitride layer or silicon oxynitride layer.
7. The method as recited in claim 3 , wherein the third insulation layer is formed of BSG, PSG, BPSG, APL or HDP oxide.
8. The method as recited in claim 1 , further comprising a step of forming a plug in the contact hole.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
December 3, 2002
March 9, 2004
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