A switching unit, equipped with a plurality of port cards and a plurality of switch cards connected in a non-parallel fashion to the port cards. Each port card has a first M-way commutator and a second M-way commutator, wherein the total number of first M-way commutators over all the port cards is N and wherein the total number of second M-way commutators over all the port cards is also N. Each switch card has a first N-way commutator and a second N-way commutator, wherein the total number of first N-way commutators over all the switch cards is M and wherein the total number of second N-way commutators over all the switch cards is also M. Each switch card further has a unit for controllably time switching a plurality of signals output by each first N-way commutator and providing a plurality of switched signals to the corresponding second N-way commutator. The mth output of the nth first M-way commutator is connected to the nth input of the mth first N-way commutator and the nth output of the mth second N-way commutator is connected to the mth input of the nth second M-way commutator, for 1<=m<=M and 1<=n<=N. The commutators and the time switching units cooperate to provide non-blocking time and space switching of signals at the inputs of the first M-way commutators.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A switching unit, comprising: a plurality of port cards, each port card comprising at least one first M-way commutator and a corresponding number of second M-way commutators, wherein the first M-way commutators over all the port cards range from a 1 st first M-way commutator to an Nth first M-way commutator and wherein the second M-way commutators over all the port cards range from a 1 st second M-way commutator to an Nth second M-way commutator; and a plurality of switch cards, each switch card comprising at least one first N-way commutator and a corresponding number of second N-way commutators, wherein the first N-way commutators over all the switch cards range from a 1 st first N-way commutator to an Mth first N-way commutator and wherein the second N-way commutators over all the switch cards range from a 1 st second N-way commutator to an Mth second N-way commutator, each switch card further comprising a time switch for controllably interchanging portions of signals present at the outputs of the at least one first N-way commutator on that switch card, and for providing switched signals to the inputs of the at least one second N-way commutator on that switch card; wherein the mth output of the nth first M-way commutator is connected to the nth input of the mth first N-way commutator and wherein the nth output of the mth second N-way commutator is connected to the mth input of the nth second M-way commutator, for 1< m< M and 1< n< N.
2. A switching unit as claimed in claim 1 , wherein the M-way commutators and the N-way commutators have harmonically related commutation step rates, whereby the first M-way commutators on the port cards and the first N-way commutators on the switch cards work as a P-way commutator and whereby the second M-way commutators on the port cards and the second N-way commutators on the switch cards work as a P-way commutator, where P M*N.
3. A switching unit as claimed in claim 1 , wherein the port cards are substantially parallel to one another, wherein the switch cards are substantially parallel to one another and wherein a normal to any port card and a normal to any switch card are not parallel.
4. A switching unit as claimed in claim 1 , wherein the port cards are substantially parallel to one another, wherein the switch cards are substantially parallel to one another and wherein the port cards are substantially orthogonal to the switch cards.
5. A switching unit as claimed in claim 1 , wherein all the commutators and the time switches in each switch card cooperate to provide non-blocking time and space switching of signals at the inputs of the first M-way commutators.
6. A switching unit as claimed in claim 1 , further comprising a mid-plane connected to the port cards and to the switch cards, wherein connections between the first M-way commutators and the first N-way commutators and connections between the second N-way commutators and the second M-way commutators are provided by electrical paths through the mid-plane.
7. A switching unit as claimed in claim 1 , further comprising a control unit connected to the port cards and to the switch card, wherein the control unit is adapted to provide synchronization of the commutators on the port cards and on the switch cards.
8. A switching unit as claimed in claim 6 , further comprising a control unit connected to the port cards and to the switch card, wherein the control unit is adapted to provide synchronization of the commutators on the port cards and on the switch cards.
9. A switching unit as claimed in claim 8 , wherein the control unit is connected to the port cards and to the switch cards through respective electrical traces through the mid-plane.
10. A switching unit as claimed in claim 1 , wherein the each port card further comprises a receive processing section connected to the input of the respective first M-way commutator and a transmit processing section connected to the output of the respective second M-way commutator.
11. A switching unit as claimed in claim 10 , wherein the receive processing section comprises opto-electronic conversion circuitry, for converting a plurality of optical signals into M electrical signals fed to respective inputs of the respective first M-way commutator.
12. A switching unit as claimed in claim 11 , wherein the receive processing section further comprises a processing and conditioning unit connected between the opto-electronic conversion circuitry and the respective first M-way commutator, comprising circuitry for decoding control information contained in the frames of incoming signals.
13. A switching unit as claimed in claim 10 , wherein the transmit processing section comprises opto-electronic conversion circuitry, for converting a plurality of signals received from the second M-way commutator into a plurality of optical signals.
14. A switching unit as claimed in claim 13 , wherein the transmit processing section further comprises a processing and conditioning unit connected between the respective second M-way commutator and the opto-electronic conversion circuitry, comprising circuitry for encoding control information into the frames of outgoing signals.
15. A switching unit as claimed in claim 12 , wherein at least one of the processing and conditioning units further comprises circuitry for extracting a clock signal from incoming signals.
16. A switching unit as claimed in claim 1 , wherein the time switch on each switch card comprises a plurality N of data memories and a plurality N of connection memories, wherein each data memory comprises an addressable memory store adapted to write data received from the first N-way commutator into a sequential memory locations and further adapted to read data at a memory location specifiable by the connection memory and further adapted to supply the read data to the second N-way commutator.
17. A switching unit as claimed in claim 16 , wherein the M-way commutators have a first commutation step rate and the N-way commutators have a second commutation step rate harmonically related to the first commutation step rate, each switch card further comprising means connected to the connection memories, for changing the connection memories at a rate equal to the faster of the first and second commutation step rates.
18. A switching unit as claimed in claim 1 , each switch card further comprising a serial-to-parallel interface between the respective first N-way commutator and the respective time switch and a parallel-to-serial interface between the respective time switch and the respective second N-way commutator.
19. A switching unit as claimed in claim 1 , further comprising at least one spare card identical in structure to, and connected in parallel with, the port cards, for providing the functionality of a port card in case of failure of a port card.
20. A switching unit as claimed in claim 19 , wherein upon failure of a port card, the first N-way commutator on each switch card is programmable to receive data from one of the spare cards instead of the failed port card.
21. A switching unit as claimed in claim 19 , wherein upon failure of a port card, the second N-way commutator on each switch card is programmable to send data to one of the spare cards instead of the failed port card.
22. A switching unit as claimed in claim 19 , further comprising a micro-electro-mechanical switch for rerouting external traffic to and from one of the spare cards in case of a port card failure.
23. A switching unit as claimed in claim 1 , further comprising at least one spare card identical in structure to, and connected in parallel with, the switch cards, for providing the functionality of a switch card in case of failure of a switch card.
24. A switching unit as claimed in claim 23 , wherein upon failure of a switch card, the first M-way commutator on each port card is programmable to send data to one of the spare cards instead of the failed switch card.
25. A switching unit as claimed in claim 23 , wherein upon failure of a switch card, the second M-way commutator on each port card is programmable to receive data from one of the spare cards instead of the failed switch card.
26. A switching unit, comprising: a plurality of receive port cards, each receive port card comprising at least one first M-way commutator, wherein the first M-way commutators over all the receive port cards range from a 1 st first M-way commutator to an Nth first M-way commutator; a plurality of transmit port cards, each transmit port card comprising at least one second M-way commutator, wherein the second M-way commutators over all the transmit port cards range from a 1 st second M-way commutator to an Nth second M-way commutator; a plurality of switch cards, each switch card comprising at least one first N-way commutator and a corresponding number of second N-way commutators, wherein the first N-way commutators over all the switch cards range from a 1 st first N-way commutator to an Mth first N-way commutator and wherein the second N-way commutators over all the switch cards range from a 1 st second N-way commutator to an Mth second N-way commutator, each switch card further comprising a time switch for controllably interchanging portions of signals present at the outputs of the at least one first N-way commutator on that switch card, and for providing switched signals to the inputs of the at least one second N-way commutator on that switch card; wherein the mth output of the nth first M-way commutator is connected to the nth input of the mth first N-way commutator and wherein the nth output of the mth second N-way commutator is connected to the mth input of the nth second M-way commutator, for 1< m< M and 1< n< N.
27. A switching unit as claimed in claim 26 , wherein the M-way commutators and the N-way commutators have harmonically related commutation step rates, whereby the first M-way commutators on the receive port cards and the first N-way commutators on the switch cards work as a P-way commutator and whereby the second M-way commutators on the transmit port cards and the second N-way commutators on the switch cards work as a P-way commutator, where P M*N.
28. A switching unit as claimed in claim 26 , wherein the receive port cards are substantially parallel to one another, wherein the transmit port cards are substantially parallel to one another, wherein the switch cards are substantially parallel to one another, wherein the normal to any receive port card and the normal to any switch card are not parallel and wherein the normal to any transmit port card and the normal to any switch card are not parallel.
29. A switching unit as claimed in claim 26 , wherein the receive port cards are substantially parallel to one another, wherein the transmit port cards are substantially parallel to one another, wherein the switch cards are substantially parallel to one another and wherein the receive port cards are substantially orthogonal to the switch cards and wherein the transmit port cards are substantially orthogonal to the switch cards.
30. A switching unit as claimed in claim 26 , wherein all the commutators and the means for controllably time switching cooperate to provide non-blocking time and space switching of signals at the inputs of the first M-way commutators.
31. A switching unit as claimed in claim 26 , further comprising a first mid-plane connected to the receive port cards and to the switch cards and a second mid-plane connected to the transmit port cards and to the switch cards, wherein the connections between the first M-way commutators and the first N-way commutators are provided by electrical paths through the first mid-plane and the connections between the second N-way commutators and the second M-way commutators are provided by electrical paths through the second mid-plane.
32. A port card, comprising: a connector for connecting the port card to a plurality of switch cards; at least one first M-way commutator and a corresponding number of second M-way commutators, the connector being connected to the outputs of the at least one first M-way commutator and to the inputs of the second M-way commutators, the first and second M-way commutators having a common commutation step rate controllable by a sequencing signal; and a sequencing unit connected to the connector and to the first and second M-way commutators, for generating the sequencing signal as a function of a clock signal received from the connector.
33. A circuit card, comprising: a connector distributed along an edge of the circuit card; a first commutator having a plurality of outputs connected to the connector; a second commutator having a plurality of inputs connected to the connector; wherein the first and second commutators cooperate with a plurality of other commutators and a distributed time switch to provide non-blocking time and space switching of signals at the inputs to the first commutator.
34. A switch card, comprising: a connector for connecting the switch card to a plurality of port cards; at least one first commutator and a corresponding number of second commutators, the connector being connected to the inputs of the at least one first commutator and to the outputs of the second commutators, the first and second commutators having a common commutation step rate controllable by a sequencing signal; means for controllably time switching a plurality of signals output by each first commutator and for providing a plurality of switched signals to the corresponding second commutator; and a sequencing unit connected to the connector and to the first and second commutators, for generating the sequencing signal as a function of a clock signal received from the connector.
35. A circuit card, comprising: a connector disposed along an edge of the circuit card; a first commutator having a plurality of inputs connected to the connector; a second commutator having a plurality of outputs connected to the connector; a time switch comprising a plurality of randomly addressable data memories connected between respective outputs of the first commutator and respective inputs of the second commutator; wherein the randomly addressable data memories are accessed according to a time-varying connection map; whereby the time switch cooperates with other time switches and the first and second commutators cooperate with other commutators to provide non-blocking time and space switching of a plurality of input signals.
36. A compound commutator, comprising: a plurality of M-way commutators distributed among a plurality of substantially parallel first circuit cards, wherein the M-way commutators over all the first circuit cards range from a 1 st M-way commutator to an Nth M-way commutator, and wherein the M-way commutators have a common first commutation step rate; and a plurality of N-way commutators distributed among a plurality of substantially parallel second circuit cards, wherein the N-way commutators over all the second circuit cards range from a 1 st N-way commutator to an Mth N-way commutator, and wherein the N-way commutators have a common second commutation step rate; wherein the mth output of the nth M-way commutator is connected to the nth input of the mth N-way commutator for all 1< m< M and 1< n< N; wherein the first and second commutation step rates are harmonically related; and wherein a normal to any first circuit card and a normal to any second circuit card are not parallel.
37. A compound commutator as claimed in claim 36 , wherein the plurality of second circuit cards are disposed obliquely with respect to the first circuit cards.
38. A compound commutator as claimed in claim 36 , wherein the plurality of second circuit cards are disposed substantially orthogonally with respect to the first circuit cards.
39. A compound commutator as claimed in claim 36 , wherein the first commutation step rate is equal to M times the second commutation step rate.
40. A compound commutator as claimed in claim 39 , wherein the compound commutator has a commutation step rate equal to the first commutation step rate.
41. A compound commutator as claimed in claim 36 , wherein the second commutation step rate is equal to N times the first commutation step rate.
42. A compound commutator as claimed in claim 41 , wherein the compound commutator has a commutation step rate equal to the second commutation step rate.
43. A compound commutator as claimed in claim 36 , wherein any of the first commutators is itself an M-way compound commutator.
44. A compound commutator as claimed in claim 36 , wherein any of the second commutators is itself an N-way compound commutator.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 2, 2000
March 9, 2004
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