A disk drive system is disclosed that includes a disk device coupled to control circuitry. The control circuitry encodes data using a modulo code. The control circuitry separates the data into blocks and encodes the data by inserting stuff bits between blocks according to the modulo code. The control circuitry converts the encoded data into a write signal and transfers the write signal to the disk device. The control circuitry also receives a read signal from the disk device and converts the read signal into a data signal. The data signal represents blocks of data separated by stuff bits. The control circuitry detects errors in a block of data by determining the modulo value of the block of data and the following stuff bits.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A disk drive system comprising: a disk device configured to receive a write signal and store corresponding data to a storage media, and to read the storage media and transfer a corresponding read signal; and control circuitry configured to receive a first data block and a second data block, insert first stuff bits between the first data block and the second data block to give a first modulo value to a first extended data block comprised of the first data block and the first stuff bits, convert the first extended data block into the write signal, transfer the write signal, receive the read signal, convert the read signal into a data signal representing a second extended data block comprised of a third data block and second stuff bits, and detect errors in the third data block by determining a second modulo value of the second extended data block.
2. The disk drive system in claim 1 wherein the modulo-values are modulo-three values.
3. The disk drive system in claim 2 wherein the modulo-three values equal zero.
4. The disk drive system in claim 1 wherein the control circuitry is further configured to preserve a D 1 constraint.
5. The disk drive system in claim 1 wherein the control circuitry is further configured to use non-return to zero invertive (NRZI) transition encoding.
6. The disk drive system in claim 1 wherein the control circuitry is further configured to change the timing of the transitions in a digital signal representing the first extended data block.
7. The disk drive system in claim 1 wherein the control circuitry is further configured to sample the read signal to generate read samples.
8. The disk drive system in claim 7 wherein the control circuitry is further configured to adaptively filter the read samples to generate equalized samples.
9. The disk drive system in claim 8 wherein the control circuitry is further configured to interpolate the equalized samples to generate interpolated samples.
10. The disk drive system in claim 9 wherein the control circuitry is further configured to detect an encoded bit stream in the interpolated samples.
11. The disk drive system in claim 10 wherein the control circuitry is further configured to decode the encoded bit stream into the data signal.
12. Disk drive control circuitry comprising: a write channel circuit configured to receive a first data block and a second data block, insert first stuff bits between the first data block and the second data block to give a first modulo value to a first extended data block comprised of the first data block and the first stuff bits, convert the first extended data block into a write signal, and transfer the write signal; and a read channel circuit configured to receive a read signal, convert the read signal into a data signal representing a second extended data block comprised of a third data block and second stuff bits, and detect errors in the third data block by determining a second modulo value of the second extended data block.
13. The disk drive control circuitry in claim 12 wherein the modulo values are modulo-three values.
14. The disk drive control circuitry in claim 13 wherein the modulo-three values equal zero.
15. The disk drive control circuitry in claim 12 wherein the write channel circuit is further configured to preserve a D 1 constraint.
16. The disk drive control circuitry in claim 12 wherein the write channel circuit is further configured to use non-return to zero invertive (NRZI) transition encoding.
17. The disk drive control circuitry in claim 12 wherein the write channel circuit is further configured to change the timing of the transitions in a digital signal representing the first extended data block.
18. The disk drive control circuitry in claim 12 wherein the read channel circuit is further configured to sample the read signal to generate read samples.
19. The disk drive control circuitry in claim 18 wherein the read channel circuit is further configured to adaptively filter the read samples to generate equalized samples.
20. The disk drive control circuitry in claim 19 wherein the read channel circuit is further configured to interpolate the equalized samples to generate interpolated samples.
21. The disk drive control circuitry in claim 20 wherein the read channel circuit is further configured to detect an encoded bit stream in the interpolated samples.
22. The disk drive control circuitry in claim 21 wherein the read channel circuit is further configured to decode the encoded bit stream into the data signal.
23. A write channel circuit comprising: an encoder configured to receive a first data block and a second data block, insert stuff bits between the first data block and the second data block to give a set modulo value to an extended data block comprised of the first data block and the stuff bits, and transfer the extended data block on a digital signal; a write compensation circuit configured to receive the digital signal, change the timing of the transitions in the digital signal, and transfer the digital signal; and an interface configured to receive the digital signal, convert the digital signal into an analog write signal, and transfer the write signal.
24. The write channel circuit in claim 23 wherein the modulo value is a modulo-three value.
25. The write channel circuit in claim 24 wherein the modulo-three value equals zero.
26. The write channel circuit in claim 23 wherein the encoder is further configured to preserve a D 1 constraint.
27. The write channel circuit in claim 23 wherein the encoder is further configured to use non-return to zero invertive (NRZI) transition encoding.
28. A read channel circuit comprising: a sampling circuit configured to receive and sample a read signal to generate read samples; an adaptive filter configured to receive and shape the read samples to generate equalized samples; an interpolated timing recovery (I.T.R.) circuit configured to receive and interpolate the equalized samples to generate interpolated samples; a detector configured to receive the interpolated samples and detect an encoded bit stream in the interpolated samples; and a decoder configured to receive the encoded bit stream, decode the encoded bit stream into a data signal representing an extended data block comprised of a first data block and stuff bits, and detect errors in the first data block by determining a modulo value of the extended data block.
29. The read channel circuit in claim 28 wherein the modulo value is a modulo-three value.
30. The read channel circuit in claim 29 wherein the modulo-three value equals zero.
31. A method for operating a disk drive system, the method comprising: inserting first stuff bits between a first data block and a second data block to give a first modulo value to a first extended data block comprised of the first data block and the first stuff bits; transferring a write signal representing the first extended data block; transferring a read signal representing a second extended data block comprised of a third data block and second stuff bits; and detecting errors in the third data block by determining a second modulo value of the second extended data block.
32. The method in claim 31 wherein the modulo values are modulo-three values.
33. The method in claim 32 wherein the modulo-three values equal zero.
34. The method in claim 31 further including preserving a D 1 constraint.
35. The method in claim 31 further including using non-return to zero invertive (NRZI) transition encoding.
36. The method in claim 31 further including changing the timing of the transitions in a digital signal representing the first extended data block.
37. The method in claim 31 further including converting the first extended data block into the write signal.
38. The method in claim 31 further including sampling the read signal to generate read samples.
39. The method in claim 38 further including adaptively filtering the read samples to generate equalized samples.
40. The method in claim 39 further including interpolating the equalized samples to generate interpolated samples.
41. The method in claim 40 further including detecting an encoded bit stream in the interpolated samples.
42. The method in claim 41 further including decoding the encoded bit stream into a data signal representing the second extended data block.
43. A method for operating disk drive control circuitry, the method comprising: inserting first stuff bits between a first data block and a second data block to give a first modulo value to a first extended data block comprised of the first data block and the first stuff bits; transferring a write signal representing the first extended data block; receiving a read signal representing a second extended data block comprised of a third data block and second stuff bits; and detecting errors in the third data block by determining a second modulo value of the second extended data block.
44. The method in claim 43 wherein the modulo values are modulo-three values.
45. The method in claim 43 wherein the modulo-three values equal zero.
46. The method in claim 43 further including preserving a D 1 constraint.
47. The method in claim 43 further including using non-return to zero invertive (NRZI) transition encoding.
48. The method in claim 43 further including changing the timing of the transitions in a digital signal representing the first extended data block.
49. The method in claim 43 further including converting the first extended data block into the write signal.
50. The method in claim 43 further including sampling the read signal to generate read samples.
51. The method in claim 50 further including adaptively filtering the read samples to generate equalized samples.
52. The method in claim 51 further including interpolating the equalized samples to generate interpolated samples.
53. The method in claim 52 further including detecting an encoded bit stream in the interpolated samples.
54. The method in claim 53 further including decoding the encoded bit stream into a data signal representing the second extended data block.
55. A method for operating a write channel circuit, the method comprising: receiving a first data block and a second data block; inserting stuff bits between the first data block and the second data block to give a set modulo value to an extended data block comprised of the first data block and the stuff bits; converting the extended data block into a write signal; and transferring the write signal.
56. The method in claim 55 wherein the modulo value is a modulo-three value.
57. The method in claim 55 wherein the modulo-three value equals zero.
58. The method in claim 55 further including preserving a D 1 constraint.
59. The method in claim 55 further including using non-return to zero invertive (NRZI) transition encoding.
60. The method in claim 55 further including changing the timing of the transitions in a digital signal representing the extended data block.
61. A method for operating a read channel circuit, the method comprising: receiving a read signal representing an extended data block comprised of a first data block and stuff bits; converting the read signal into a data signal representing the extended data block; and detecting errors in first data block by determining a modulo value, of the extended data block.
62. The method in claim 61 wherein the modulo value is a modulo-three value.
63. The method in claim 61 wherein the modulo-three value equals zero.
64. The method in claim 61 further including preserving a D 1 constraint.
65. The method in claim 61 further including using non-return to zero invertive (NRZI) transition encoding.
66. The method in claim 61 further including sampling the read signal to generate read samples.
67. The method in claim 66 further including adaptively filtering the read samples to generate equalized samples.
68. The method in claim 67 further including interpolating the equalized samples to generate interpolated samples.
69. The method in claim 68 further including detecting an encoded bit stream in the interpolated samples.
70. The method in claim 69 further including decoding the encoded bit stream into the data signal.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 3, 2000
March 16, 2004
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.