An apparatus and method for controlling a refresh operation of a memory device capable of performing an internal refresh after a power-up sequence is completed. The apparatus an apparatus for controlling a refresh operation of a memory device comprising DRAM memory cells and a SRAM interface, comprises a control circuit for outputting a control signal in a second state in response to a power-up signal during a predetermined period, the second state for disabling refresh operations, and for outputting the control signal in a first state in response to a command signal, wherein the command signal is a first active command input signal after the predetermined period, and a refresh pulse generating circuit for outputting a pulse signal for refreshing the DRAM memory cells in response to the control signal in the first state.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An apparatus for controlling a refresh operation of a memory device comprising DRAM memory cells and a SRAM interface, comprising: a control circuit for outputting a control signal in a second state in response to a power-up signal during a predetermined period, the second state for disabling refresh operations, and for outputting the control signal in a first state in response to a command signal, wherein the command signal is a first active command input signal after the predetermined period; and a refresh pulse generating circuit for outputting a pulse signal for refreshing the DRAM memory cells in response to the control signal in the first state.
2. The apparatus of claim 1 , wherein the control circuit comprises: a node; a first element for pulling down the node to a logic low in response to the power-up signal; a second element for pulling up the node to a logic high in response to the command signal; and a third element for inverting the logic level at the node to generate the control signal.
3. The apparatus of claim 2 , wherein the first element comprises: a first inverter for receiving the power-up signal; and an NMOS transistor comprising a gate connected to an output terminal of the first inverter, a drain connected to the node, and a source connected to ground.
4. The apparatus of claim 2 , wherein the second element comprises: a second inverter for receiving the command signal; and a PMOS transistor comprising a gate connected to an output terminal of the second inverter, a source connected to power, and a drain connected to the node.
5. The apparatus of claim 2 , wherein the control circuit further comprises a latch element for holding the logic level of the node.
6. The apparatus of claim 5 , wherein the latch element comprises: a third inverter comprising an input terminal connected to the node; and a fourth inverter comprising an output terminal connected to the node, and an input terminal connected to an output terminal of the third inverter.
7. The apparatus of claim 1 , wherein the command signal comprises one of a read command and a write command.
8. The apparatus of claim 1 , wherein the predetermined period is a period from a time when an external power voltage reaches steady state, to a time when a predetermined time elapses.
9. The apparatus of claim 1 , wherein the command signal generates a pulse signal, and wherein the control circuit outputs the control signal in the first state in response to the pulse signal.
10. A memory device comprising DRAM cells, comprising: a control circuit for generating a control signal in response to a data write/read command, wherein the command is the first input signal after a power-up sequence is completed; and a refresh pulse generating circuit for generating a pulse signal for refreshing the DRAM cells in response to the control signal.
11. The device of claim 10 , wherein the power-up sequence is a period from a time when an external power voltage reaches steady state, to a time when a predetermined time elapses.
12. The device of claim 10 , wherein the command generates a predetermined pulse signal, wherein the control circuit generates the control signal in response to the pulse signal.
13. A method for controlling a refresh operation of a memory device comprising DRAM memory cells and an SRAM interface, comprising: outputting a control signal in a second state during a predetermined period in response to a power-up signal; outputting the control signal in a first state in response to a command signal, wherein the command signal is a first active command input signal after the predetermined period; and outputting a pulse signal for refreshing the DRAM memory cells in response to the control signal in the first state.
14. The method of claim 13 , wherein the predetermined period is a period from a time when the power-up signal is reaches a target level, to a time when a predetermined time elapses.
15. The method of claim 13 , wherein the outputting the control signal in the second state comprises: outputting a voltage having a logic low level, when a voltage level of the power-up signal is lower than a predetermined voltage level; and inverting the logic low level of the voltage to a logic high level to generate the control signal in the second state.
16. The method of claim 13 , wherein the outputting the control signal in the first state comprises: outputting a voltage having a logic high level in response to the command signal; and inverting the logic high level of the voltage to a logic low level to generate the control signal in the first state.
17. The method of claim 13 , wherein the command signal generates a predetermined pulse, and wherein the control signal is generated in response to the predetermined pulse.
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July 25, 2002
March 16, 2004
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