Method and apparatus for passive component minimization of connector pins in a computer system

1. In a computer, a passive component minimization of connector pins configuration comprising: a daughterboard including at least one selection switch coupled via passive components to a single connector pin of a first origin, the at least one selection switch for selectively connecting the passive components to the single connector pin representative of a prescribed state of a number of states of said daughterboard, the prescribed state of the number of states being selectable as a function of the at least one selection switch and the passive components; and a motherboard including a supply voltage and pull-up resistor circuit coupled to a single connector pin of a second origin, said motherboard further including decoding circuitry coupled to the motherboard connector pin for decoding a voltage level of the motherboard connector pin into binary data, wherein responsive to a mating of the daughterboard connector pin with the motherboard connector pin, the decoding circuitry converts voltage level data present at the motherboard connector pin into binary data representative of a current state of said daughterboard as a function of the at least one selection switch and passive components of said daughterboard.

2. The configuration of claim 1 , wherein the decoding circuitry includes first, second, and third op-amps, the first op-amp having a non-inverting input coupled to the motherboard connector pin and an inverting input coupled to a first reference voltage, the second op-amp having an inverting input coupled to the motherboard connector pin and a non-inverting input coupled to a second reference voltage, and the third op-amp having an inverting input coupled to the motherboard connector pin and a non-inverting input coupled to a third reference voltage, the decoding circuitry further including a logical AND gate for logically ANDing outputs of the first and third op-amp, wherein an output of the second op-amp and an output of the AND gate represent two bits for defining four possible states.

3. The configuration of claim 2 , wherein the voltage supply includes a 5 volt supply and the pull-up resistor includes a 1 kohm resistor.

4. The configuration of claim 2 , wherein the first reference potential includes a nominal 0.5 V potential, the second reference potential includes a a nominal 2.0 V potential, and the third reference potential includes a nominal 3.0 V potential.

5. The configuration of claim 1 , wherein the passive components of said daughterboard include three series connected resistors collectively coupled at a first end thereof to the daughterboard connector pin and wherein the at least one selection switch includes four switches, a first switch being coupled between the daughterboard connector pin and ground potential, the second switch coupled between the first and second of the three series connected resistors and ground potential, the third switch coupled between the second and third of the three series connected resistors and ground potential, and a fourth switch coupled between a second end of the series connected resistors opposite the first end and ground potential.

6. The configuration of claim 5 , wherein the first resistor includes a nominal 333 ohm resistor, the second resistor includes a nominal 667 ohm resistor, and the third resistor includes a nominal 2 kohm resistor.

7. The configuration of claim 1 , wherein the passive components of said daughterboard include three series connected resistors collectively coupled at a first end thereof to the daughterboard connector pin and wherein the at least one selection switch includes a single switch having four positions, a first position for coupling the daughterboard connector pin directly to ground potential, a second position for coupling the daughterboard connector pin to ground potential via a first of the three series connected resistors, a third position for coupling the daughterboard connector pin to ground potential via the first and a second resistor of the three series connected resistors, and a fourth position for coupling the daughterboard connector pin to ground potential via the first, second, and a third resistor of the three series connected resistors.

8. The configuration of claim 1 , wherein said daughterboard is a single-sided printed circuit board characterized by through hole, passive components.

9. A method for passive component minimization of connector pins comprising: coupling at least one selection switch via passive components to a single connector pin of a daughterboard, the connector pin being of a first origin and the at least one selection switch for selectively connecting the passive components to the single connector pin representative of a prescribed state of a number of states of the daughterboard, the prescribed state of the number of prescribed states being selectable as a function of the at least one selection switch and the passive components; coupling a supply voltage and pull-up resistor circuit to a single connector pin of a motherboard, the connector pin being of a second origin; and coupling decoding circuitry to the motherboard connector pin for decoding a voltage level of the motherboard connector pin into binary data, wherein responsive to a mating of the daughterboard connector pin with the motherboard connector pin, the decoding circuitry converts voltage level data present at the motherboard connector pin into binary data representative of a current state of the daughterboard as a function of the at least one selection switch and passive components of the daughterboard.

10. The method of claim 9 , wherein coupling decoding circuitry to the motherboard connector pin includes coupling decoding circuitry having first, second, and third op-amps, the first op-amp having a non-inverting input coupled to the motherboard connector pin and an inverting input coupled to a first reference voltage, the second op-amp having an inverting input coupled to the motherboard connector pin and a non-inverting input coupled to a second reference voltage, and the third op-amp having an inverting input coupled to the motherboard connector pin and a non-inverting input coupled to a third reference voltage, the decoding circuitry further including a logical AND gate for logically ANDing outputs of the first and third op-amp, wherein an output of the second op-amp and an output of the AND gate represent two bits for defining four possible states.

11. The method of claim 10 , wherein the voltage supply includes a 5 volt supply and the pull-up resistor includes a 1 kohm resistor.

12. The method of claim 10 , wherein the first reference potential includes a nominal 0.5 V potential, the second reference potential includes a nominal 2.0 V potential, and the third reference potential includes a nominal 3.0 V potential.

13. The method of claim 9 , wherein coupling the at least one selection switch via passive components includes coupling three series connected resistors collectively at a first end thereof to the daughterboard connector pin and wherein the at least one selection switch includes four switches, a first switch being coupled between the daughterboard connector pin and ground potential, the second switch coupled between the first and second of the three series connected resistors and ground potential, the third switch coupled between the second and third of the three series connected resistors and ground potential, and a fourth switch coupled between a second end of the series connected resistors opposite the first end and ground potential.

14. The method of claim 13 , wherein the first resistor includes a nominal 333 ohm resistor, the second resistor includes a nominal 667 ohm resistor, and the third resistor includes a nominal 2 kohm resistor.

15. The method of claim 9 , wherein coupling the at least one selection switch via passive components includes coupling three series connected resistors collectively at a first end thereof to the daughterboard connector pin and wherein the at least one selection switch includes a single switch having four positions, a first position for coupling the daughterboard connector pin directly to ground potential, a second position for coupling the daughterboard connector pin to ground potential via a first of the three series connected resistors, a third position for coupling the daughterboard connector pin to ground potential via the first and a second resistor of the three series connected resistors, and a fourth position for coupling the daughterboard connector pin to ground potential via the first, second, and a third resistor of the three series connected resistors.

16. The method of claim 9 , wherein the daughterboard is a single-sided printed circuit board characterized by through hole, passive components.

17. An apparatus having a passive component minimization of connector pins configuration comprising: a secondary printed circuit board including at least one selection switch coupled via passive components to a single connector pin of a first origin, the at least one selection switch for selectively connecting the passive components to the single connector pin representative of a prescribed state of a number of states of said secondary printed circuit board, the prescribed state of the number of prescribed states being selectable as a function of the at least one selection switch and the passive components; and a primary printed circuit board including a supply voltage and pull-up resistor circuit coupled to a single connector pin of a second origin, said primary circuit board further including decoding circuitry coupled to the primary circuit board connector pin for decoding a voltage level of the primary circuit board connector pin into binary data, wherein responsive to a mating of the secondary printed circuit board connector pin with the primary printed circuit board connector pin, the decoding circuitry converts voltage level data present at the primary printed circuit board connector pin into binary data representative of a current state of said secondary printed circuit board as a function of the at least one selection switch and passive components of said secondary printed circuit board.

18. The apparatus of claim 17 , wherein the decoding circuitry includes first, second, and third op-amps, the first op-amp having a non-inverting input coupled to the primary printed circuit board connector pin and an inverting input coupled to a first reference voltage, the second op-amp having an inverting input coupled to the primary printed circuit board connector pin and a non-inverting input coupled to a second reference voltage, and the third op-amp having an inverting input coupled to the primary printed circuit board connector pin and a non-inverting input coupled to a third reference voltage, the decoding circuitry further including a logical AND gate for logically ANDing outputs of the first and third op-amp, wherein an output of the second op-amp and an output of the AND gate represent two bits for defining four possible states.

19. The apparatus of claim 17 , wherein the passive components of said secondary printed circuit board include three series connected resistors collectively coupled at a first end thereof to the secondary printed circuit board connector pin and wherein the at least one selection switch includes four switches, a first switch being coupled between the secondary printed circuit board connector pin and ground potential, the second switch coupled between the first and second of the three series connected resistors and ground potential, the third switch coupled between the second and third of the three series connected resistors and ground potential, and a fourth switch coupled between a second end of the series connected resistors opposite the first end and ground potential.

20. The apparatus of claim 17 , wherein the passive components of said secondary printed circuit board include three series connected resistors collectively coupled at a first end thereof to the secondary printed circuit board connector pin and wherein the at least one selection switch includes a single switch having four positions, a first position for coupling the secondary printed circuit board connector pin directly to ground potential, a second position for coupling the secondary printed circuit board connector pin to ground potential via a first of the three series connected resistors, a third position for coupling the secondary printed circuit board connector pin to ground potential via the first and a second resistor of the three series connected resistors, and a fourth position for coupling the secondary printed circuit board connector pin to ground potential via the first, second, and a third resistor of the three series connected resistors.

21. The apparatus of claim 17 , wherein said secondary printed circuit board is a single-sided printed circuit board characterized by through hole, passive components.