A system having multiple encoders of different maximum error correction capability, which reduces the entire size of the system by allowing most of the system to be shared among these encoders. This is accomplished by using an encoder that is capable of calculating parities of 2 or more kinds of bit numbers with different error correction capability. The system includes a circuit that generates a modified word by assigning a predetermined value to input an information word; and a circuit that generates an intermediate signal “u” by a linear operation using a modified word and matrix “P”. These circuits are combined with linear operation circuits for generating value of parity p1, . . . , p&agr;, each of whose bit number is different, by a linear operation using all or part of the intermediate signal and matrixes Q1, . . . , Q&agr; respectively.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An encoder that calculates parities of (here, is an integer of 2 or more) kinds of bit numbers with different error correction capability, comprising: a first encoder/decoder circuit for generating a modified word by assigning a predetermined value to shared input information word having at least two kinds of messages; a second circuit connected to said first circuit for generating an intermediate signal u by linear operation using said modified word and a matrix P; and a third circuit connected to said second circuit having linear circuits for generating value of parity p 1 , . . . , p a , each of whose bit number is different, by linear operations using all or part of the intermediate signal u and a plurality of matrixes Q 1 , . . . , Q a respectively, wherein P*Q forms a generator matrix G for each error correction.
2. The encoder according to claim 1 wherein said first circuit generates a modified word by assigning a predetermined value to an appropriate position in the shared input information word so that it will be a word of the same bit number whatever parity is generated.
3. The encoder according to claim 2 , having maximum adjustment circuits for adjusting the bit number of said intermediate signal corresponding to each of the third linear circuits.
4. The encoder according to claim 3 , wherein said matrixes Q 1 , . . . , Q a are all square matrixes.
5. The encoder according to claim 4 , wherein bit length of said predetermined value is equal to or larger than the largest bit length of said value parity p 1 , . . . , p a .
6. The encoder according to claim 5 , wherein said predetermined value is zero vector.
7. The encoder according to claim 6 , wherein said intermediate signal is smaller in bit length than said modified word.
8. The encoder according to claim 7 , wherein said linear operation is based on a Galois field or Galois extension field.
9. A circuit having a single encoder and decoder that calculates parities of (here, is an integer of 1 or more) kinds of bit numbers for a set of 1-dimensional linear error correction codes with different error correction capability, said circuit comprising: a first encoder/decoder circuit for generating a modified word by inserting a predetermined value if a shared input message is an information word with at least two messages without any parity; a second circuit connected to said first circuit for generating an intermediate signal u by a linear operation using said modified word and a matrix P; a third circuit connected to said second circuit having operation circuits for generating a syndrome value of s 1 , . . . , s a , by a linear operation using all or part of the intermediate signal and a plurality of matrixes R 1 , . . . , R a respectively; and a fourth circuit connected to said second circuit having a linear operation circuits for generating a value of parity p 1 , . . . , p a , each of whose bit number is different, by a linear operation using all or part of said intermediate signal u and a plurality of matrixes Q 1 , . . . , Q a , respectively, wherein P*R forms a check matrix H and P*Q forms a generator matrix G for each linear error correction code.
10. The circuit according to claim 9 , wherein said matrixes R 1 , . . . , R a are all square matrixes.
11. A circuit having a single encoder and decoder that calculates parities of (here, is an integer of 1 or more) kinds of bit numbers for a set of 1-dimensional linear error correction codes with different error correction capability, said circuit comprising: a first encoder/decoder circuit for generating a modified word by assigning a predetermined value if a shared input message is an information word without any parity; a second circuit connected to said first circuit for generating an intermediate signal u by a linear operation using said modified word and a matrix P; a third circuit connected to said second circuit having a plurality of syndrome circuits for generating a syndrome value of s 1 , . . . , s a by linear operation using all or part of said intermediate signal u and a plurality of matrixes R; and a fourth circuit connected to said second circuit having circuits for generating a value of parity p 1 , . . . , p a each of whose bit number is different, by linear operation using all or part of said intermediate signal u and a plurality of matrixes Q 1 , . . . , Q a respectively wherein P*Q forms a generator matrix G for each of the error correction codes and P*R forms a check matrix H that calculates the syndrome value of s 1 , . . . , s a .
12. The circuit according to claim 11 , having an adjustment circuit for adjusting bit number of said intermediate signal corresponding to the third or fourth circuit.
13. A circuit having a single encoder and decoder capable of calculating parities of (here, is an integer of 1 or more) kinds of bit numbers for a set of 1-dimensional linear correction codes with different error correction capability, said circuit comprising: a first encoder/decoder circuit for generating a modified word by assigning a predetermined value if shared input message is an information word without any parity; a second circuit connected to said first circuit for generating an intermediate signal by a linear operation using said modified word and a matrix P, said intermediate signal having a syndrome value of s 1 , . . . , s a if said input message is a received word; and a third circuit connected to said second circuit having operation circuits for generating a value of parity p 1 , . . . , p a , each of whose bit number is different, by linear operation using all or part of said intermediate signal and a plurality of matrixes Q 1 , . . . , Q a respectively wherein P*Q forms a generator maxtrix G for each of said linear correction codes.
14. The circuit according to claim 13 , having an adjustment circuit for adjusting a bit number of said intermediate signal corresponding to the third circuit.
15. The circuit according to claim 14 wherein said first circuit, when the information word or received word has a bit number which is less than received a word of a larger length is input, generates a modified word by assigning a predetermined value to an appropriate position in such word so that it will be a word of the same bit number.
16. The circuit according to claim 15 , wherein said matrixes Q 1 , . . . , Q a are all square matrixes.
17. The circuit according to claim 16 , wherein bit length of said predetermined value is equal to or larger than the largest bit length of said value of parity p 1 , . . . , p a .
18. The circuit according to claim 17 , wherein said predetermined value is zero vector.
19. The circuit according to claim 18 , wherein said intermediate signal is smaller in bit length than said modified word.
20. The circuit according to claim 19 , wherein said linear operation is linear operation on Galois field or Galois extension field.
21. A method of generating parities of (here, is an integer of 2 or more) kinds of bit numbers with different error correction capability, comprising the steps of: sharing input information with encoding and decoding circuits; generating a modified word by inserting a predetermined value to input information word; generating an intermediate signal u by a linear operation using said modified word and a matrix P; and generating a value of parity p 1 , . . . , p a , each of whose bit number is different, by a linear operation using all or part of the intermediate signal and a plurality of matrixes Q 1 , . . . , Q a respectively.
22. A storage medium for storing a program for generating parities of (here, is an integer of 2 or more) kinds of bit numbers with different error correction capability, said program comprising the steps of: sharing input information with encoding and decoding circuits; generating a modified word by assigning a predetermined value to input information word; generating an intermediate signal u by a linear operation using said modified word and a matrix P; and generating a value of parity p 1 , . . . , p a , each of which is a different bit number, by a linear operation using all or part of the intermediate signal and a plurality of matrixes Q 1 , . . . , Q a respectively.
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April 6, 2000
April 13, 2004
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