A sense amplifier circuit includes first and second amplifier circuits. The first amplifier circuit includes a pair of cross-coupled transistors of a first channel type (e.g., N-channel FETs), and the second amplifier circuit includes a pair of cross-coupled transistors of a second channel type (e.g., P-channel FETs). The sense amplifier circuit also includes a third transistor of the second channel type coupled between first nodes of the first and second amplifier circuits, and a fourth transistor of the second channel type coupled between second nodes of the first and second amplifier circuits. The sense amplifier circuit reduces access device leakage of a DRAM cell during LRL refresh access, and improves refresh margin on a DRAM cell with a one written thereto. A method of reducing access device leakage and improving refresh margin using such an improved sense amplifier is also described.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A sense amplifier circuit, comprising: an N-sense amplifier connected a first digit line and a second digit line; a P-sense amplifier connected the first digit line and the second digit line; and a limit circuit connected to the N-sense amplifier and the P-sense amplifier and operable for limiting the lowest voltage on the first digit line during an access cycle to a non-zero voltage.
2. The sense amplifier according to claim 1 wherein the limit circuit limits the lowest voltage on the first digit line to one transistor threshold voltage (V TH ) above zero volts.
3. The sense amplifier according to claim 2 wherein the limit circuit limits the lowest voltage on the first digit line to one P-channel transistor threshold voltage (V TH ) above zero volts.
4. The sense amplifier according to claim 1 wherein the limit circuit is further operable for driving the lowest voltage on the first digit line during an equilibrate cycle to zero voltages.
5. A sense amplifier circuit for limiting leakage in non-selected memory cells on a selected digit line, comprising: an N-sense amplifier; a P-sense amplifier connected to a first digit line and a second digit line; a first transistor connected between the N-sense amplifier and the first digit line; a second transistor connected between the N-sense amplifier and the second digit line; and a limit circuit connected to the first transistor and the second transistor and operable for limiting the lowest voltage on the first digit line to a non-zero voltage during an access cycle.
6. The sense amplifier according to claim 5 wherein the limit circuit limits the lowest voltage on the first digit line to one transistor threshold voltage (V TH ) above zero volts while the second digit line is at a supply voltage.
7. The sense amplifier according to claim 5 wherein the limit circuit is further operable for driving the lowest voltage on the first digit line during an equilibrate cycle to zero volts to produce a one half supply voltage on the first and second digit lines.
8. A sense amplifier circuit for limiting leakage in non-selected memory cells on a selected digit line, comprising: an N-sense amplifier; a P-sense amplifier connected to a first digit line and a second digit line; a first transistor connected between the N-sense amplifier and the first digit line; a second transistor connected between the N-sense amplifier and the second digit line; and a limit signal connected to the first transistor and the second transistor, the limit signal being zero volts to limit the lowest voltage on the first digit line to one transistor threshold voltage (V TH ) above zero volts during an access cycle, and the limit signal being a negative voltage to force the first digit line to zero volts during an equilibrate cycle.
9. The sense amplifier according to claim 8 wherein the first transistor and the second transistor are p-channel transistors and the one transistor threshold voltage (V TH ) is one p-channel transistor threshold voltage.
10. A DRAM sense amplifier circuit for limiting access transistor leakage on non-selected memory cells on a digit line shared with an accessed memory cell, comprising: a cross-coupled N-sense amplifier; a cross-coupled P-sense amplifier connected to a true digit line and a complement digit line; a first p-channel transistor connected between the N-sense amplifier and the true digit line; a second transistor connected between the N-sense amplifier and the complement digit line; and a limit signal connected to the first transistor and the second transistor and operable for limiting the lowest voltage on the true digit line or the complement digit line to a non-zero voltage during an access cycle.
11. The sense amplifier according to claim 10 wherein the lowest voltage on the true digit line or the complement digit line is one transistor threshold voltage above zero volts.
12. The sense amplifier according to claim 11 wherein the highest voltage on the true digit line or the complement digit line is the supply voltage (V CC ).
13. The sense amplifier according to claim 10 wherein the limit signal is a negative voltage to force the true digit line and the complement digit line to V CC /2 during an equilibrate cycle.
14. A DRAM memory device, comprising: a plurality of 1T1C (one transistor, one capacitor) memory cells sharing a common digit line and having separate wordlines; a sense amplifier connected to the common digit line, and having an N-sense amplifier connected to the digit line and to a reference digit line and a P-sense amplifier connected the digit line and the reference digit line; and a limit circuit connected to the sense amplifier and operable for limiting the lowest voltage on the digit line to a non-zero voltage during an access cycle.
15. The memory device according to claim 14 wherein the lowest voltage on the digit line is one transistor threshold voltage above zero volts.
16. The memory device according to claim 15 wherein the highest voltage on the digit line is the supply voltage (V CC ).
17. The memory device according to claim 16 wherein the limit circuit is further operable for forcing the digit line and the reference digit line to V CC /2 during an equilibrate cycle.
18. A DRAM sense amplifier circuit for limiting access transistor leakage on non-selected memory cells on a digit line shared with an accessed memory cell, comprising: an N-sense amplifier connected a first digit line and a second digit line; a P-sense amplifier connected the first digit line and the second digit line; and a limit signal connected to the N-sense amplifier and the P-sense amplifier, the limit signal being zero volts to limit the lowest voltage on the first digit line to one transistor threshold voltage (V TH ) above zero volts during an access cycle, and the limit signal being a negative voltage to force the first digit line to zero volts during an equilibrate cycle.
19. A DRAM sense amplifier circuit for limiting access transistor leakage on non-selected memory cells on a digit line shared with an accessed memory cell, comprising: an N-sense amplifier; a P-sense amplifier connected the first digit line and the second digit line; and a first transistor connected between the N-sense amplifier and the first digit line; a second transistor connected between the N-sense amplifier and the second digit line; and a limit signal connected to the first transistor and the second transistor, the limit signal being zero volts (V SS ) to limit the lowest voltage on the first digit line to one transistor threshold voltage (V TH ) above zero volts during an access cycle.
20. The sense amplifier according to claim 19 wherein the limit signal is a negative voltage (V BB ) to force the first digit line to zero volts during an equilibrate cycle.
21. A DRAM sense amplifier circuit, comprising: a cross-coupled N-sense amplifier having a first cross-coupling node and a second cross-coupling node; a cross-coupled P-sense amplifier connected to a true digit line and a complement digit line and cross coupled with the first cross-coupling node and the second cross-coupling node of the N-sense amplifier; a first limit transistor connected between the first cross-coupling node of the N-sense amplifier and the true digit line; a second limit transistor connected between the second cross-coupling node of the N-sense amplifier and the complement digit line; and a limit signal connected to the first limit transistor and the second limit transistor and operable for limiting the lowest voltage on the true digit line or the complement digit line to a non-zero voltage during an access cycle.
22. The sense amplifier according to claim 21 wherein the limit signal is zero volts to limit the lowest voltage on the true digit line or the complement digit line to one transistor threshold voltage (V TH ) above zero volts during an access cycle.
23. The sense amplifier according to claim 21 wherein the limit signal is a negative voltage to force the true digit line and the complement digit line to one-half the supply voltage (V CC /2) during an equilibrate cycle.
24. A DRAM sense amplifier, comprising: a true digit line ( 726 A) and a complement digit line ( 726 B); a first transistor ( 816 A) having a first source/drain node connected to a first sense amplifier control input (PSA), having a second source/drain node ( 818 A) connected to the true digit line, and having a gate connected to a second internal node ( 812 B); a second transistor ( 816 B) having a first source/drain node connected to the first sense amplifier control input (PSA), having a second source/drain node connected to the complement digit line, and having a gate connected to a first internal node ( 812 A); a third transistor ( 810 A) having a first source/drain node connected to a second sense amplifier control input (NSA), having a second source/drain node connected to the first internal node ( 812 A), and having a gate connected to the second internal node ( 812 B); a fourth transistor ( 810 B) having a first source/drain node connected to the second sense amplifier control input (NSA), having a second source/drain node connected to the second internal node ( 812 B), and having a gate connected to the first internal node ( 812 A); a fifth transistor ( 806 ) having a first source/drain node connected to the true digit line ( 818 A), having a second source/drain node connected to the first internal node ( 812 A), and having a gate connected to a limit signal ( 822 ); a sixth transistor ( 808 ) having a first source/drain node connected to the complement digit line ( 818 B), having a second source/drain node connected to the second internal node ( 812 B), and having a gate connected to the limit signal ( 822 ); and a limit generation circuit for generating the limit signal.
25. The DRAM sense amplifier of claim 24 wherein the limit signal is zero volts during an access cycle, and the limit signal is less than zero volts during an equilibrate cycle.
26. The DRAM sense amplifier of claim 24 wherein the limit signal is zero volts to limit the lowest voltage on the first digit line to one transistor threshold voltage (V TH ) above zero volts during an access cycle, and the limit signal being a negative voltage (V BB ) to force the first digit line to zero volts during an equilibrate cycle.
27. A method of sensing a memory cell in a memory circuit, comprising: accessing a memory cell to generate a differential voltage signal between a true digit line and a complement digit line; forcing the true digit line to the supply voltage; and limiting the complement digit line to a non-zero voltage.
28. The method according to claim 27 wherein limiting includes limiting the complement digit line on one transistor threshold voltage above zero volts to limit access transistor leakage from non-selected memory cells on a selected digit line.
29. A method of operating a memory cell in a memory circuit, comprising: equilibrating the true digit line and the compliment digit line to VCC/2; accessing a memory cell to generate a differential voltage signal between a true digit line and a complement digit line; forcing the true digit line to the supply voltage; and limiting the complement digit line to a non-zero voltage.
30. A method of sensing a memory cell in a memory circuit while limiting access transistor leakage from non-selected memory cells on a selected digit line, comprising: sensing the differential voltage signal between a selected digit line and a non-selected digit line using a sense amplifier circuit which includes an N-sense amplifier and a P-sense amplifier, wherein the sensing includes: firing the N-sense amplifier to discharge the low voltage on the true digit line towards ground; firing the P-sense amplifier to charge the higher voltage on the complement digit line toward the supply voltage; and limiting the discharge of the low voltage on the true digit line to prevent the low voltage digit line from reaching ground.
31. The method according to claim 30 wherein limiting includes limiting the low voltage on the true digit line on one transistor threshold voltage above zero volts to limit access transistor leakage from non-selected memory cells on a selected digit line.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 18, 2003
April 27, 2004
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