In accordance with one embodiment of the present invention, a memory array includes a plurality of memory cells, the memory cells each comprising one or more gates, and a word line for controlling the gates of the plurality of memory cells. A driver is coupled to the word line at a first location. The driver is operable to drive the gates of the memory cells. A load device is coupled to the word line at a second location remote from the first location. The load device is operable to pull a set of gates electrically isolated from the driver to a substantially non-floating state.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory device, comprising: a plurality of memory cells, the memory cells each comprising one or more gates; a word line for controlling the gates of the plurality of memory cells; a driver coupled to the word line at a first location, the drivers operable to drive the gates of the plurality of memory cells; and a load device coupled to a second location of the word line remote from the first location, and operable to pull one or more of the plurality of memory cells electrically isolated from the driver to a non-floating state.
2. The memory device of claim 1 , wherein the memory device is a static random-access memory device.
3. The integrated circuit of claim 1 , wherein the word line comprises a metal film.
4. The integrated circuit of claim 1 , wherein the load device comprises a diode.
5. The integrated circuit of claim 1 , wherein the load device comprises a current source.
6. The integrated circuit of claim 5 , wherein the operation of the current source is regulated by the addressing logic.
7. The integrated circuit of claim 1 , wherein the load device is a pull-down device.
8. The integrated circuit of claim 1 , wherein the load device is a pull-up device.
9. A method for pulling electrically isolated memory cells in a memory array to a non-floating state, comprising: providing a memory device, the memory device comprising: a plurality of memory cells, the memory cells each comprising one or more gates controlled by a word line; a driver coupled to a first location of the word line for driving the gates of the plurality of memory cells; and a load device coupled to a second location of the word line remote from the first location; and pulling with the load device one or more of the plurality of memory cells electrically isolated from the driver to a non-floating state.
10. The method of claim 9 , wherein the load device comprises a diode.
11. The method of claim 9 , wherein the load device comprises a current source.
12. The method of claim 11 , wherein the operation of the current source is regulated by the addressing logic.
13. The method of claim 9 , wherein the load device is a pull-down device.
14. The method of claim 9 , wherein the load device is a pull-up device.
15. The method of claim 9 , wherein the word line comprises a metal film.
16. A static random access memory device, comprising: a plurality of memory cells, the memory cells each comprising one or more gates; a word line comprising a metal film for controlling the gates of the plurality of memory cells; a driver coupled to a first location of the word line for driving the gates of the plurality of memory cells; and a load device coupled to a second location of the word line remote from the first location, and operable to pull one or more of the plurality of memory cells electrically isolated from the driver to a non-floating state.
17. The static random access memory device of claim 16 , wherein the load device comprises a pull-down device.
18. The static random access memory device of claim 16 , wherein the load device comprises a pull-up device.
19. The static random access memory device of claim 16 , wherein the load device comprises a diode.
20. The static random access memory device of claim 16 , wherein the load device comprises a current source.
21. The static random access memory device of claim 20 , wherein the operation of the current source is regulated by the addressing logic.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
September 10, 2002
May 11, 2004
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.