A semiconductor device has a gate-insulating film formed on a semiconductor substrate. Gate electrodes comprised of P- and N-type polysilicon thin films and thin conductive films are formed over the gate-insulating film. The P- and N-type polysilicon thin films are doped with impurities at an impurity concentration sufficient to prevent depletion layers from being formed in the P- and N-type polysilicon thin films when a voltage is applied between each of the conductive thin films and the semiconductor substrate. Source and drain regions are formed over the semiconductor substrate in spaced-apart relation to one another and on opposite sides of the gate electrodes.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: a gate-insulating film formed on a semiconductor substrate; a plurality of gate electrodes comprised of P- and N-type polysilicon thin films and thin conductive films formed over the gate-insulating film, the P-type polysilicon thin film being doped with a P-type impurity at a concentration in excess of 2E19 atoms/cm 3 and the N-type polysilicon thin film being doped with an N-type impurity at a concentration in excess of 2E19 atoms/cm 3 to prevent depletion layers from being formed in the P- and N-type polysilicon thin films when a voltage is applied between each of the conductive thin films and the semiconductor substrate; and source and drain regions formed over the semiconductor substrate in spaced-apart relation to one another and disposed on opposite sides of the gate electrodes.
2. A semiconductor device comprising: a gate insulating film disposed on a surface of a semiconductor substrate; a gate electrode disposed on the gate insulating film and having a polysilicon film containing B or BF 2 impurity ions and a silicide film disposed on the polysilicon film; a dielectric film disposed over the whole surface of the semiconductor substrate and the gate electrode; and source and drain regions containing B or BF 2 impurity ions and disposed in the surface of the semiconductor substrate.
3. A semiconductor device according to claim 2 ; further comprising a planarized BPSG interlayer film disposed on the dielectric film.
4. A semiconductor device according to claim 2 ; wherein the dielectric film comprises a CVD-grown dielectric film having a thickness of 5 to 1000 .
5. A semiconductor device according to claim 2 ; wherein the gate insulating film has a thickness of 30 to 200 ; and wherein the gate electrode has a minimum length of 1.0 m.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 15, 2002
May 25, 2004
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