In a trench (2), an oxynitride film (31ON1) and a silicon oxide film (31O1) are positioned between a doped silicon oxide film (31D) and a substrate (1), and a silicon oxide film (31O2) is positioned closer to the entrance of the trench (2) than the doped silicon oxide film (31D). The oxynitride film (31ON1) is formed by a nitridation process utilizing the silicon oxide film (31O1). The vicinity of the entrance of the trench (2) is occupied by the silicon oxide films (31O1, 31O2) and the oxynitride film (31ON1).
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: a semiconductor substrate having a main surface and a trench, said trench having an entrance formed in said main surface; a doped insulator doped with impurities and disposed in said trench; an undoped insulator not being doped with impurities and disposed in said trench, said undoped insulator being positioned opposite to a bottom surface of said trench with said doped insulator interposed therebetween; a first oxynitride film disposed in said trench between said doped insulator and said semiconductor substrate and between said undoped insulator and said semiconductor substrate; and a second oxynitride film disposed between said doped insulator and said undoped insulator, wherein said doped insulator is isolated from said semiconductor substrate by said undoped insulator and said first oxynitride film.
2. The semiconductor device according to claim 1 , further comprising a silicon oxide film disposed between said first oxynitride film and said semiconductor substrate, wherein said first oxynitride film is formed by a nitridation process that utilizes said silicon oxide film.
3. The semiconductor device according to claim 2 , further comprising an MIS-type transistor disposed in an area on said main surface of said semiconductor substrate where said trench is absent.
4. The semiconductor device according to claim 1 , wherein said impurities in said doped insulator comprise at least one element among fluorine, boron, phosphorus, arsenic, chlorine, iodine, and bromine.
5. The semiconductor device according to claim 4 , further comprising an MIS-type transistor disposed in an area on said main surface of said semiconductor substrate where said trench is absent.
6. The semiconductor device according to claim 1 , further comprising an MIS-type transistor disposed in an area on said main surface of said semiconductor substrate where said trench is absent.
7. A semiconductor device comprising: a semiconductor substrate having a main surface and a trench, said trench having an entrance formed in said main surface; a doped insulator doped with impurities and disposed in said trench; an undoped insulator not being doped with impurities and disposed in said trench, said undoped insulator being positioned opposite to a bottom surface of said trench with said doped insulator interposed therebetween; a silicon oxide film disposed in said trench between said doped insulator and said semiconductor substrate; an oxynitride film disposed in said trench between said undoped insulator and said semiconductor substrate and between said undoped insulator and said doped insulator; and second oxynitride film disposed between said doped insulator and said undoped insulator, wherein said doped insulator is isolated from said semiconductor substrate by said silicon oxide film, said undoped insulator and said oxynitride film.
8. The semiconductor device according to claim 7 , wherein said impurities in said doped insulator comprise at least one element among fluorine, boron, phosphorus, arsenic, chlorine, iodine, and bromine.
9. The semiconductor device according to claim 8 , further comprising an MIS-type transistor disposed in an area on said main surface of said semiconductor substrate where said trench is absent.
10. The semiconductor device according to claim 7 , further comprising an MIS-type transistor disposed in an area on said main surface of said semiconductor substrate where said trench is absent.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 4, 2003
June 1, 2004
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