Device layout to improve ESD robustness in deep submicron CMOS technology

1. A method of forming ESD-protection MOS transistors with an active region comprising: forming gate electrodes of the ESD-protection MOS transistors with the gate electrodes being of uniform narrow width across the entire active region aside from the periphery thereof, and forming gate electrodes with wider ends at the periphery of the active region, whereby the transistors have improved turn-on uniformity.

2. The method of claim 1 wherein the ESD protection transistors are NMOS transistors and PMOS transistors.

3. The method of claim 1 wherein source contacts and drain contacts for transistors are located inboard of the periphery of the active region leaving space for the wider ends of the gate electrodes at the periphery of the active region.

4. The method of claim 1 wherein the active region has peripheral boundaries, and the wider ends of the gate electrodes straddle the peripheral boundaries of the active region.

5. The method of claim 1 including: forming inner NMOS transistors and outer NMOS transistors and inner PMOS transistors and outer PMOS transistors in high-voltage-tolerant I/O circuits, and forming the wider ends on only the inner NMOS transistors and the inner PMOS transistors.

6. A method of forming a layout for ESD-protection MOS transistors comprising: forming gate electrodes of the ESD-protection MOS transistors with an active region having peripheral boundaries, and with the gate electrodes being of uniform narrow width in the active region aside from the periphery thereof, and forming some of the gate electrodes with asymmetric wider ends at the periphery of the active region, whereby the transistors have improved turn-on uniformity.

7. The method of claim 6 wherein the ESD protection transistors are NMOS transistors and PMOS transistors.

8. The method of claim 6 wherein source contacts and drain contacts for the transistors are located inboard of the periphery of the active region leaving space for the wider ends of the gate electrodes.

9. The method of claim 6 wherein the wider ends of the gate electrodes straddle the peripheral boundaries of the active region.

10. The method of claim 6 wherein a modified layout style is provided for inner and outer NMOS transistors and PMOS transistors in the high-voltage-tolerant I/O circuits with the wider ends being provided on only the inner NMOS transistors and PMOS transistors.

11. A layout form of ESD-protection MOS transistors comprising gate electrodes of the ESD-protection MOS transistors formed with the gate electrodes being of uniform narrow width in an active region thereof aside from the periphery thereof, and some of the gate electrodes having wider ends at the periphery of the active region, whereby the transistors have improved turn-on uniformity.

12. The layout of claim 11 wherein the ESD protection transistors are NMOS transistors and PMOS transistors.

13. The layout of claim 11 wherein source contacts and drain contacts for transistors are located inboard of the periphery of the active region leaving space for the wider ends of the gate electrodes.

14. The layout of claim 11 wherein the active region has peripheral boundaries, and the wider ends of the gate electrodes straddle the peripheral boundaries of the active region.

15. The layout of claim 11 wherein a modified layout style is provided for inner and outer NMOS transistors and PMOS transistors in the high-voltage-tolerant I/O circuits with the wider ends being provided on only the inner NMOS transistors and PMOS transistors.

16. A layout form ESD-protection MOS transistors comprising: gate electrodes of the ESD-protection MOS transistors formed with an active region having peripheral boundaries, the gate electrodes being of uniformly narrow width in the active region aside from the periphery thereof, and some of the gate electrodes having asymmetric wider ends at the periphery of the active region, whereby the transistors have improved turn-on uniformity.

17. The layout of claim 16 wherein the ESD protection transistors are NMOS transistors and PMOS transistors.

18. The layout of claim 16 wherein source contacts and drain contacts for the transistors are located inboard of the periphery of the active region leaving space for the wider ends of the gate electrodes.

19. The layout of claim 16 wherein the wider ends of the gate electrodes straddle the peripheral boundaries of the active region.

20. The layout of claim 16 wherein a modified layout style is provided for inner and outer NMOS transistors and PMOS transistors in the high-voltage-tolerant I/O circuits with the wider ends being provided on only the inner NMOS transistors and PMOS transistors.

21. A layout form of ESD-protection MOS transistors comprising: an active region with parallel rows of contacts including source contacts, the rows of source contacts and drain contacts for the transistors being located inboard of the periphery of the active region, with pairs of rows of drain contacts formed adjacent, gate electrodes of the ESD-protection MOS transistors formed parallel with the rows of contacts with the gate electrodes being of uniformly narrow width in an active region thereof aside from the periphery thereof, and some of the gate electrodes having wider ends at the periphery of the active region, whereby the transistors have improved turn-on uniformity.

22. The layout of claim 21 wherein the gate electrode proximate to rows of source contacts have narrow ends at the periphery of the active region and the gate electrodes proximate to rows of drain contacts have widened ends at the periphery of the active region.

23. The layout of claim 21 wherein the gate electrode proximate to rows of source contacts have narrow ends at the periphery of the active region and the gate electrodes proximate to rows of drain contacts have widened ends at the periphery of the active region only on the sides proximate to the rows of drain contacts.