A chip repair system designed for automated test equipment independent application on many unique very dense ASIC devices in a high turnover environment is disclosed. During test, the system will control on chip built-in self-test (BIST) engines collect and compress repair data, program fuses and finally decompress and reload the repair data for post fuse testing. In end use application this system decompresses and loads the repair data at power-up or at the request of the system.
Legal claims defining the scope of protection, as filed with the USPTO.
1. An application specific integrated circuit (ASIC) chip comprising: memory elements; a plurality of fuses connected to said memory elements and being adapted to be programmed to replace defective memory elements with replacement memory elements; and a fuse controller connected to said fuses and being adapted to program said fuses, wherein said fuse controller has a standardized test interface protocol for an external tester, such that said tester is presented with the same interface protocol irrespective of a design of said ASIC chip.
2. The ASIC chip in claim 1 , wherein said fuse controller includes an instruction processor adapted to decode instructions from said tester.
3. The ASIC chip in claim 1 , wherein said fuse controller includes a repair data processing unit adapted to program said fuses.
4. The ASIC chip in claim 1 , further comprising built-in-self-test (BIST) units connected to said memory elements and said fuse controller, said BIST units being adapted to test said memory elements.
5. The ASIC chip in claim 4 , wherein said fuse controller includes a repair data processing unit adapted to initiate said BIST units.
6. The ASIC chip in claim 5 , further comprising repair registers connected to said BIST units and being adapted to store compressed repair data relating to said defective memory elements.
7. The ASIC chip in claim 6 , wherein a count of repairs needed in said repair registers determines a time needed to program said fuses.
8. The ASIC chip in claim 5 , wherein said repair data processing unit is further adapted to read and decompress fuse data prior to initiating said BIST units.
9. The ASIC chip in claim 5 , wherein said repair data processing unit is further adapted to collect and compress repair data after said BIST units test said memory elements.
10. The ASIC chip in claim 1 , wherein said fuses comprise e-fuses.
11. A fuse controller for use on an application specific integrated circuit (ASIC) chip, said fuse controller comprising: an instruction processor adapted to decode instructions from an external tester; and a repair data processing unit connected to said instruction processor and being adapted to program fuses to replace defective memory elements with replacement memory elements on said ASIC; and wherein said fuse controller has a standardized test interface protocol for an external tester, such that said tester is presented with the same interface protocol irrespective of a design of said ASIC chip.
12. The fuse controller in claim 11 , wherein said repair data processing unit is adapted to initiate built-in-self-test (BIST) units connected to memories on said ASIC and said fuse controller, said BIST units being adapted to test said memory elements.
13. The fuse controller in claim 12 , wherein said repair data processing unit is adapted to initiate said BIST units.
14. The fuse controller in claim 12 , wherein said repair data processing unit is further adapted to read and decompress fuse data prior to initiating said BIST units.
15. The fuse controller in claim 12 , wherein said repair data processing unit is further adapted to collect and compress repair data after said BIST units test said memory elements.
16. The fuse controller in claim 11 , wherein said repair data processing unit is further adapted to store compressed repair data relating to said defective memory elements in repair registers.
17. The fuse controller in claim 16 , wherein a count of repairs needed in said repair registers determines a time needed to program said fuses.
18. The fuse controller in claim 11 , wherein said fuses comprise e-fuses.
19. A method for programming fuses to replace defective memory elements with replacement memory elements on an application specific integrated circuit (ASIC) chip, said method comprising: issuing instructions from an external tester to a fuse controller on said ASIC chip, wherein said fuse controller has a standardized test interface protocol, such that said tester is presented with the same interface protocol irrespective of a design of said ASIC chip; decoding said instructions using said fuse controller; testing memory elements on said ASIC to identify said defective memory elements using said fuse controller; and programming said fuses using said fuse controller.
20. The method in claim 19 , wherein said decoding is performed using an instruction processor within said fuse controller.
21. The method in claim 19 , wherein said programming of said fuses is performed using a repair data processing unit within said fuse controller.
22. The method in claim 21 , wherein said testing comprises initiating built-in-self-test (BIST) units using said repair data processing unit.
23. The method in claim 22 , further comprising reading and decompressing fuse data prior to initiating said BIST units using said repair data processing unit.
24. The method in claim 21 , further comprising storing compressed repair data relating to said defective memory elements in repair registers.
25. The method in claim 24 , further comprising determining a time needed to program said fuses based on said lengths of said repair registers.
26. The method in claim 21 , further comprising, after said testing of said memory elements, collecting and compressing repair data using said repair data processing unit.
27. An integrated circuit chip comprising: a plurality of fuses adapted to be programmed to replace defective memory elements with replacement memory elements on said chip; and a fuse controller connected to said fuses and being adapted to program said fuses, wherein said fuse controller has a standardized test interface protocol for an external tester, such that said tester is presented with the same interface protocol irrespective of a design of said chip.
28. The chip in claim 27 , wherein said fuse controller includes an instruction processor adapted to decode instructions from said tester.
29. The chip in claim 27 , wherein said fuse controller includes a repair data processing unit adapted to program said fuses.
30. The chip in claim 27 , further comprising built-in-self-test (BIST) units connected to said fuse controller, said BIST units being adapted to test memory elements.
31. The chip in claim 30 , wherein said fuse controller includes a repair data processing unit adapted to initiate said BIST units.
32. The chip in claim 31 , further comprising repair registers connected to said BIST units and being adapted to store compressed repair data relating to said defective memory elements.
33. The chip in claim 32 , wherein a count of repairs needed in said repair registers determines a time needed to program said fuses.
34. The chip in claim 31 , wherein said repair data processing unit is further adapted to read and decompress fuse data prior to initiating said BIST units.
35. The chip in claim 31 , wherein said repair data processing unit is further adapted to collect and compress repair data after said BIST units test said memory elements.
36. The chip in claim 27 , wherein said fuses comprise e-fuses.
37. An application specific integrated circuit (ASIC) chip comprising: memory elements; a plurality of fuses connected to said memory elements and being adapted to be programmed to replace defective memory elements with replacement memory elements; and a fuse controller connected to said fuses, wherein said fuse controller comprises: a standardized test interface protocol for an external tester, such that said tester is presented with the same interface protocol irrespective of a design of said ASIC chip, an instruction processor adapted to decode instructions from said tester; and a repair data processing unit adapted to program said fuses.
38. The ASIC chip in claim 37 , further comprising built-in-self-test (BIST) units connected to said memory elements and said fuse controller, said BIST units being adapted to test said memory elements.
39. The ASIC chip in claim 38 , wherein said repair data processing unit is adapted to initiate said BIST units.
40. The ASIC chip in claim 38 , further comprising repair registers connected to said BIST units and being adapted to store compressed repair data relating to said defective memory elements.
41. The ASIC chip in claim 40 , wherein a count of repairs needed in said repair registers determines a time needed to program said fuses.
42. The ASIC chip in claim 38 , wherein said repair data processing unit is further adapted to read and decompress fuse data prior to initiating said BIST units.
43. The ASIC chip in claim 38 , wherein said repair data processing unit is further adapted to collect and compress repair data after said BIST units test said memory elements.
44. The ASIC chip in claim 37 , wherein said fuses comprise e-fuses.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 7, 2002
July 27, 2004
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