Semiconductor device less susceptible to variation in threshold voltage

1. A semiconductor device, comprising: a differential amplifier for amplifying a difference between a first input potential and a second input potential, said differential amplifier including a first MOS (Metal Oxide Semiconductor) transistor determining a bias current of said differential amplifier; and a threshold compensating circuit configured for compensating a fluctuation of a threshold voltage of a MOS transistor, said threshold compensating circuit including, a diode circuit having a bipolar transistor for generating a constant voltage, and a MOS transistor circuit comprised of MOS transistors for providing voltage higher than said constant voltage by a prescribed voltage.

2. The semiconductor device according to claim 1 , further comprising: a load circuit; and a second MOS transistor coupled between an externally applied first power supply potential and a second power supply potential and having its gate potential controlled according to an output of said differential amplifier, for supplying said second power supply potential resulting from down-converting said first power supply potential to said load circuit, wherein said first input potential is a reference potential, and said second input potential is an internal potential according to said second power supply potential.

3. The semiconductor device according to claim 2 , wherein said diode circuit includes first and second diode circuits, said MOS transistor circuit includes a third MOS transistor, and a fourth MOS transistor forming a current mirror pair with said third MOS transistor, said first diode circuit is connected in series with said third MOS transistor, and said second diode circuit is connected in series with said fourth MOS transistor.

4. The semiconductor device according to claim 3 , wherein said first diode circuit includes a first diode element, and said second diode circuit includes a plurality of second diode elements connected in parallel with each other.

5. The semiconductor device according to claim 3 , wherein said first diode circuit includes a first diode element, and said second diode circuit includes a second diode element, said second diode element having a different pn junction area from that of said first diode element so that a current flowing through said first diode element multiplied by a prescribed factor flows through said second diode element when a same bias potential is applied.

6. The semiconductor device according to claim 3 , wherein said first, third and fourth MOS transistors are of a same conductivity type.

7. A semiconductor device, comprising: a threshold compensating circuit for outputting a control potential according to a threshold voltage of a MOS (Metal 0 xide Semiconductor) transistor; a differential amplifier for amplifying a difference between a reference potential and an internal potential, including a first MOS transistor receiving said control potential at its gate, for determining a bias current of said differential amplifier according to said control potential; a load circuit; and a second MOS transistor coupled between an externally applied first power supply potential and a second power supply potential and having its gate potential controlled according to an output of said differential amplifier, for supplying said second power supply potential resulting from down-converting said first power supply potential to said load circuit, wherein said internal potential is a potential according to said second power supply potential, and said threshold compensating circuit includes a plurality of third MOS transistors of a same conductivity type as that of said first MOS transistor, said plurality of third MOS transistors having substantially a same transistor size as that of said first MOS transistor and being provided near said first MOS transistor, a precharge circuit for charging respective drains of said plurality of third MOS transistors to a prescribed potential, a potential generator for applying a plurality of different potentials to respective gates of said plurality of third MOS transistors after the respective drains of said plurality of third MOS transistors are precharged to said prescribed potential, and a logic circuit for monitoring respective drain potentials of said plurality of third MOS transistors and determining said control potential based on the monitoring result.

8. The semiconductor device according to claim 7 , wherein said threshold compensating circuit further includes a potential generating portion for outputting a plurality of bias reference potentials based on said first power supply potential, and a selecting portion for selecting said control potential from said plurality of bias reference potentials according to an output of said logic circuit.

9. A semiconductor device comprising: a threshold compensating circuit for outputting a control potential according to a threshold voltage of MOS (Metal Oxide Semiconductor) transistor; a differential amplifier for amplifying a difference between a reference potential and an internal potential, including a first MOS transistor receiving said control potential at its gate for determining a bias current of said differential amplifier according to said control potential; a load circuit; and a second MOS transistor coupled between an externally applied first power supply potential and a second power supply potential and having its gate potential controlled according to an output of said differential amplifier, for supplying said second power supply potential resulting from down-converting said first power supply potential to said load circuit, wherein said internal potential is a potential according to said second power supply potential, and said threshold compensating circuit includes a third MOS transistor of a same conductivity type as that of said first MOS a third MOS transistor of a same conductivity type as that of said first MOS transistor, said third MOS transistor having substantially a same transistor size as that of said first MOS transistor and being provided near said first MOS transistor, a precharge unit for charging a drain of said third MOS transistor to a prescribed potential, a potential generator for sequentially applying a plurality of different potentials to a gate of said third MOS transistor after said drain of said third MOS transistor is precharged to said prescribed potential, and a logic circuit for monitoring a drain potential of said third MOS transistor and determining said control potential based on the monitoring result.

10. The semiconductor device according to claim 9 , wherein said threshold compensating circuit further includes a potential generating portion for outputting a plurality of bias reference potentials based an said first power supply potential, and a selecting portion for selecting said control potential from said plurality of bias reference potentials according to an output of said logic circuit.

11. The semiconductor device according to claim 2 , wherein said first MOS transistor is of a first conductivity type and:has its source coupled to a ground potential, and said differential amplifier further includes a third MOS transistor of a second conductivity type connected in series with said first MOS transistor between said first power supply potential and said ground potential, a fourth MOS transistor of said second conductivity type forming a current mirror pair with said third MOS transistor, and fifth and sixth MOS transistors receiving a current from said first power supply potential through said fourth MOS transistor, and forming a pair for differential amplification.

12. The semiconductor device according to claim 2 , wherein said first MOS transistor is of a first conductivity type and has its source coupled to a ground potential, and said differential amplifier includes third and fourth MOS transistors of said first conductivity type having their respective sources and back gates connected to a drain of said first MOS transistor, and forming a pair of differential amplification, and fifth and sixth MOS transistors of a second conductivity type having their respective drains connected to drains of said third and fourth MOS transistors, respectively, and forming a current mirror pair.

13. The semiconductor device according to claim 2 , further comprising a voltage dividing portion for dividing said second power supply potential and outputting said internal potential.

14. The semiconductor device according to claim 1 , wherein said voltage higher than said constant voltage is provided for compensating the fluctuation of the threshold voltage.