A nonvolatile ferroelectric memory includes a top cell array block and a bottom cell array block, each array block having sub cell array blocks, each sub cell array block having a plurality of unit cells; a plurality of main bitlines arranged in one direction in correspondence to a column unit of the sub cell array blocks; a plurality of sub bitlines each connected to one terminal of one of the plurality of unit cells arranged in a same direction as the one direction of the main bitlines; a sense amplifier block having sense amplifiers between the top cell array block and the bottom cell array block, each sense amplifier for amplifying a signal from the main bitline; sub bitline first switch signal application lines and sub bitline second switch signal application lines for controlling connection of the sub bitlines and the main bitlines, sub bitline pull up signal application lines for controlling pull up of the sub bitlines by a self boost operation, and sub bitline pull down signal application lines for selective pull down of the sub bitlines, which are arranged perpendicular to the sub bitlines in correspondence to the sub cell array blocks; a first switch device in each sub cell array block in correspondence to a column direction for operation under control of the sub bitline first switch signal application line; a second switch device in each sub cell array block in correspondence to a column direction for selective transfer of a signal from the sub bitline pull up signal application line to the sub bitline under the control of the sub line second switch signal application line; and, a third switch device in each sub cell array block in correspondence to a column direction for selective pull down of the sub bitline under control of the sub bitline pull down application line.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A nonvolatile ferroelectric memory comprising: a top cell array block and a bottom cell array block, each array block having sub cell array blocks, each sub cell array block having a plurality of unit cells; a plurality of main bitlines arranged in one direction in correspondence to a column unit of the sub cell array blocks; a plurality of sub bitlines each connected to one terminal of one of the plurality of unit cells arranged in a same direction as said one direction of the main bitlines; a sense amplifier block having sense amplifiers between the top cell array block and the bottom cell array block, each sense amplifier for amplifying a signal from the main bitline; sub bitline first switch signal application lines and sub bitline second switch signal application lines for controlling connection of the sub bitlines and the main bitlines, sub bitline pull up signal application lines for controlling pull up of the sub bitlines by a self boost operation, and sub bitline pull down signal application lines for selective pull down of the sub bitlines, which are arranged perpendicular to the sub bitlines in correspondence to the sub cell array blocks; a first switch device in each sub cell array block in correspondence to a column direction for operation under control of the sub bitline first switch signal application line; a second switch device in each sub cell array block in correspondence to a column direction for selective transfer of a signal from the sub bitline pull up signal application line to the sub bitline under the control of the sub line second switch signal application line; and, a third switch device in each sub cell array block in correspondence to a column direction for selective pull down of the sub bitline under control of the sub bitline pull down application line.
2. The nonvolatile ferroelectric memory as claimed in claim 1 , wherein the first switch device has a gate connected to the sub bitline first switch signal application line, and two electrodes both connected to the main bitline and the sub bitline, respectively.
3. The nonvolatile ferroelectric memory as claimed in claim 1 , wherein the second switch device has a gate connected to the sub bitline second switch signal application line, and two electrodes both connected to the sub bitline pull up line and the sub bitline, respectively.
4. The nonvolatile ferroelectric memory as claimed in claim 1 , wherein the third switch device has a gate connected to the sub bitline pull down application line, and two electrodes both connected to a ground voltage terminal and the sub bitline, respectively.
5. The nonvolatile ferroelectric memory as claimed in claim 1 , wherein each of the sub cell array blocks includes a hierarchal folded bitline cell array in which no cells overlap when the cell array is folded centered on the main bitline.
6. The nonvolatile ferroelectric memory as claimed in claim 1 , wherein each of the sub cell array blocks includes a hierarchal open bitline cell array in which cells overlap when the cell array is folded centered on the main bitline.
7. The nonvolatile ferroelectric memory as claimed in claim 1 , wherein one sense amplifier in the sense amplifier block is provided for every two main bitlines.
8. The nonvolatile ferroelectric memory as claimed in claim 1 , wherein one sense amplifier in the sense amplifier block is provided for each main bitline.
9. The nonvolatile ferroelectric memory as claimed in claim 1 , wherein each unit cell includes: the sub bitline arranged in a first direction, a wordline arranged in a second direction perpendicular to the first direction of the sub bitline, a plateline spaced from the wordline, and in the second direction, a transistor having a gate connected to the wordline, a source connected to the sub bitline, and a ferroelectric capacitor having a first terminal connected to a drain of the transistor, and a second terminal connected to the plateline.
10. The nonvolatile ferroelectric memory as claimed in claim 1 , further comprising a wordline driver shared between the sub cell array blocks for driving the wordline.
11. The nonvolatile ferroelectric memory as claimed in claim 1 , wherein the ferroelectric capacitor in the unit cell is arranged below the sub bitline and the main bitline.
12. The nonvolatile ferroelectric memory as claimed in claim 5 , wherein a cell in a row is arranged at every two columns, and a cell in a column is also arranged at every two rows in the hierarchal folded bitline cell array.
13. The nonvolatile ferroelectric memory as claimed in claim 6 , wherein a cell in a row, and a cell in a column are arranged at every one column and row in the hierarchal open bitline cell array.
14. A method for driving a nonvolatile ferroelectric memory, in which a sub bitline is enabled, and pulled up/pulled down by a self boost operation, the sub bitline being selected by a sub bitline first switching signal application line, a sub bitline second switching signal application line, a sub bitline pull up signal application line, and a sub bitline pull down signal application line, and when a continuous active period is divided into t1, t2, t3, t4, and t5 sections, and a pre-charge period is divided into t0, and t6 sections, the method comprising the steps of: (a) applying a first high level voltage to the sub bitline pull down signal application line in the t0 section, for pulling down a sub bitline and a main bitline to a low level; (b) applying a low level voltage to the sub bitline pull down signal application line in the t1 section; (c) applying a second high level voltage higher than the first high level voltage to a wordline in the t2, t3, and t4 sections, and to a plateline in the t2, and t3 sections, and applying the first high level voltage to the sub bitline first switch signal application line in the t2, and t3 sections, for transferring cell data to the sense amplifier through the sub bitline and the main bitline; (d) applying the second high level voltage to the sub bitline second switch signal application line, and transiting the plateline to the low level, both in the t4 section, and applying the second high level voltage to the sub bitline second switch signal application line in the t5 section, for self boosting the sub bitline second switch signal application line and the word line to a third high level voltage higher than the second high level voltage, thereby writing logic 1 data on a ferroelectric capacitor; and, (e) transiting the wordline and the plateline to the second high level, and applying the first high level voltage to the sub bitline first switch application line, both in the t6 section, for writing logic 0 data in the ferroelectric capacitor.
15. The method as claimed in claim 14 , wherein the second high level voltage is two times higher than the first high level voltage.
16. The method as claimed in claim 14 , wherein the self boosted third high level voltage is two times higher than the second high level voltage.
17. The nonvolatile ferroelectric memory as claimed in claim 9 , wherein the ferroelectric capacitor in the unit cell is arranged below the sub bitline and the main bitline.
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September 4, 2002
August 10, 2004
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