In a method of forming a self-aligned contact, gates are formed on a semiconductor substrate in a striped pattern. Bit lines are formed in a striped pattern that extends cross-wise to the gates. The bit lines are isolated from one another by a first interlayer insulation layer. Next, a second interlayer insulation layer is formed between the bit lines, and a photoresist film pattern is formed on the second interlayer insulation layer. The photoresist film pattern is used for forming contact holes extending between the gates down to conductive pads. The contact holes are filled to form conductive plugs that contact the conductive pads. The photoresist film pattern is formed as a series of stripes which extend parallel to the gates. The stripes of photoresist expose segments of the bit lines and the portions of the second interlayer insulation layer disposed directly above the conductive film pads, thereby securing a sufficient alignment margin, and exposing a large underlying area to be etched in forming the contact holes. To form a semiconductor device, a third interlayer insulation layer, an etch stop layer, an oxide layer and a hard mask layer are formed on the conductive plugs. Next, a second photoresist film pattern is formed on the hard mask layer. The hard mask layer and the oxide layer are etched using the second photoresist film pattern as an etching mask until the etch stop layer is exposed. Second contact holes for use in forming capacitor lower electrodes are formed by sequentially removing the exposed etching stop layer and the exposed third interlayer insulation layer using the hard mask layer as an etching mask, until the second contact holes expose the conductive plugs.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method forming self-aligned contacts, comprising the steps of: forming gate stacks in a series of parallel stripes on a semiconductor substrate; forming gate spacers on the sidewalls of the gate stacks; forming conductive film pads to serve as buried contact pads between the gate spacers; forming a first interlayer insulation layer over the conductive film pads and the gate stacks; forming bit line stacks, in a series of parallel stripes skewed relative to the gate stacks, on the first interlayer insulation layer; forming bit line spacers on the sidewalls of the bit line stacks; forming a second interlayer insulation layer on the first interlayer insulation layer in such a way that upper surfaces of the bit line stacks are exposed; forming a photoresist film pattern, on the second interlayer insulation layer, in the form of laterally spaced apart stripes of photoresist extending parallel to the gate stacks, the photoresist film pattern exposing segments of the bit line stacks and exposing portions of the second interlayer insulation layer located directly above respective ones of the conductive film pads, respectively; etching the second interlayer insulation layer and the first interlayer insulation layer using the photoresist film pattern, the bit line stacks and the bit line spacers as etching masks to form contact holes exposing the conductive film pads by; and filling the contact holes with a conductive material to form conductive plugs contacting the conductive film pads.
2. The method of claim 1 , wherein said forming of the gate stacks comprises sequentially forming a gate insulation layer, a gate conductive layer and a gate capping layer on the semiconductor substrate.
3. The method of claim 1 , wherein said forming of the bit line stacks comprises sequentially forming a barrier metal layer, a bit line conductive layer and a bit line capping layer on said first interlayer insulation layer.
4. The method of claim 1 , wherein said forming of the second interlayer insulation layer comprises forming a layer of insulation over the first interlayer insulation layer and the bit line stacks, and planarizing said layer of insulation until the upper surfaces of said bit line stacks are exposed.
5. The method of claim 4 , wherein said planarizing comprises chemical mechanical polishing.
6. The method of claim 1 , wherein said forming of the conductive plugs comprises depositing conductive material sufficient to form a layer that fills the contact holes and covers the bit line stacks, and planarizing the layer of conductive material to expose the upper surfaces of the bit line stacks.
7. The method of claim 6 , wherein said planarizing comprises an etch back technique.
8. The method of claim 6 , wherein said planarizing comprises chemical mechanical polishing.
9. A method of forming a semiconductor device, comprising the steps of: forming gate stacks in a series of parallel stripes on a semiconductor substrate; forming gate spacers on the sidewalls of the gate stacks; forming conductive film pads to serve as buried contact pads between the gate spacers; forming a first interlayer insulation layer over the conductive film pads and the gate stacks; forming bit line stacks, in a series of parallel stripes skewed relative to the gate stacks, on the first interlayer insulation layer; forming bit line spacers on the sidewalls of the bit line stacks; forming a second interlayer insulation layer on the first interlayer insulation layer in such a way that upper surfaces of the bit line stacks are exposed; forming a photoresist film pattern, on the second interlayer insulation layer, in the form of laterally spaced apart stripes of photoresist extending parallel to the gate stacks, the photoresist film pattern exposing segments of the bit line stacks and exposing portions of the second interlayer insulation layer located directly above respective ones of the conductive film pads, respectively; etching the second interlayer insulation layer and the first interlayer insulation layer using the photoresist film pattern, the bit line stacks and the bit line spacers as etching masks to form contact holes exposing the conductive film pads by; filling the contact holes with a conductive material to form conductive plugs contacting the conductive film pads; sequentially forming a third interlayer insulation layer, an etch stop layer, an oxide layer and a hard mask layer on the conductive plugs, the bit line stacks and the second interlayer insulation layer; forming a second photoresist film pattern on the hard mask layer; etching the hard mask layer and the oxide layer using the second photoresist film pattern as an etching mask until portions of the etch stop layer are exposed; subsequently removing the second photoresist film pattern; and forming second contact holes for use in forming capacitor lower electrodes by sequentially removing the exposed etch stop layer and underlying portions of the third interlayer insulation layer using the hard mask layer as an etching mask, the second contact holes exposing the conductive plugs.
10. The method of claim 9 , further comprising the step of filling the second contact holes with a conductive material to form capacitor lower electrodes contacting the conductive plugs.
11. The method of claim 9 , wherein said forming of the gate stacks comprises sequentially forming a gate insulation layer, a gate conductive layer and a gate capping layer on the semiconductor substrate.
12. The method of claim 9 , wherein said forming of the bit line stacks comprises sequentially forming a barrier metal layer, a bit line conductive layer and a bit line capping layer on the first interlayer insulation layer.
13. The method of claim 9 , wherein said forming of the second interlayer insulation comprises forming a layer of insulating material over the first interlayer insulation layer and the bit line stacks, and planarizing the layer of insulating material until upper surfaces of the bit line stacks are exposed.
14. The method of claim 13 , wherein said planarizing comprises chemical mechanical polishing.
15. The method of claim 9 , wherein said forming of the conductive plugs comprises depositing conductive material sufficient to form a layer that fills the contact holes and covers the bit line stacks, and planarizing the layer of conductive material to expose the upper surfaces of the bit line stacks.
16. The method of claim 15 , wherein said planarizing is performed using an etch back technique.
17. The method of claim 15 , wherein said planarizing comprises chemical mechanical polishing.
18. The method of claim 9 , wherein the etch stop layer is formed of a material having an etching selection ratio with respect to the oxide layer.
19. The method of claim 18 , wherein said forming of the etch stop layer comprises forming a silicon nitride layer on the third interlayer insulation layer.
20. The method of claim 9 , wherein the third interlayer insulation layer is formed of a material having an etching selection ratio with respect to the etch stop layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
May 3, 2001
August 17, 2004
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