A semiconductor memory device having MIS transistors to constitute memory cells (MC), each of the MIS transistors including a semiconductor layer (12), a source region (15) formed in the semiconductor layer, a drain region (14) formed apart from the source region in the semiconductor layer, the semiconductor layer between the source region and the drain region serving as a channel body in a floating state, a main gate (13) provided between the source region and the drain region to form a channel in the channel body; and an auxiliary gate (20) provided separately from the main gate to control a potential of the channel body by capacitive coupling, the auxiliary gate being driven in synchronization with the main gate. The MIS transistor has a first data state in which the channel body is set at a first potential and a second data state in which the channel body is set at a second potential.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor memory device having MIS transistors to constitute memory cells, each of the MIS transistors comprising: a semiconductor layer; a source region formed in the semiconductor layer; a drain region formed apart from the source region in the semiconductor layer, the semiconductor layer between the source region and the drain region serving as a channel body in a floating state; a main gate provided between the source region and the drain region to form a channel in the channel body; and an auxiliary gate provided separately from the main gate to control a potential of the channel body by capacitive coupling, the auxiliary gate being driven in synchronization with the main gate, wherein the MIS transistor has a first data state in which the channel body is set at a first potential and a second data state in which the channel body is set at a second potential.
2. The semiconductor memory device according to claim 1 , wherein the first data state is set by generating impact ionization near a drain junction by a pentode operation of the MIS transistor, and the second data state is set by passing a forward bias current between the channel body to which a predetermined potential is applied by capacitive coupling from the main gate and the drain.
3. The semiconductor memory device according to claim 1 , wherein the semiconductor layer is formed on a semiconductor substrate with an insulating film therebetween, and the main gate and the auxiliary gate are disposed to face each other on an upper face and a lower face of the semiconductor layer.
4. The semiconductor memory device according to claim 3 , wherein each of the MIS transistors further comprises a relay electrode connected to the channel body, the auxiliary gate is formed to face the relay electrode and constitute a capacitor with the relay electrode.
5. The semiconductor memory device according to claim 4 , wherein the main gate is provided between the semiconductor substrate and the semiconductor layer, and the auxiliary gate and the relay electrode are provided opposite to the main gate with the semiconductor layer therebetween.
6. The semiconductor memory device according to claim 4 , wherein the auxiliary gate and the relay electrode are provided between the semiconductor substrate and the semiconductor layer, and the main gate is provided opposite to the auxiliary gate and the relay electrode with the semiconductor layer therebetween.
7. The semiconductor memory device according to claim 1 , wherein the semiconductor layer is formed on a semiconductor substrate with an insulating film therebetween, the main gates making a pair are provided to face each other on both side faces of the channel body in the semiconductor layer, and the auxiliary gate is formed on an upper face of the semiconductor layer and electrically connects the main gates making the pair.
8. The semiconductor memory device according to claim 1 , wherein the semiconductor layer is a pillar semiconductor portion formed on a semiconductor substrate, the drain region is formed on the pillar semiconductor portion, the source region is formed under the pillar semiconductor portion, and the main gate and the auxiliary gate are provided to face each other on both side faces of the pillar semiconductor portion.
9. The semiconductor memory device according to claim 8 , wherein the main gate and the auxiliary gate are formed out of the same material.
10. The semiconductor memory device according to claim 8 , wherein the main gate and the auxiliary gate are formed out of different materials.
11. The semiconductor memory device according to claim 8 , wherein the MIS transistors are arranged in a matrix form to constitute a memory cell array, the main gates of the MIS transistors arranged in a first direction are continuously formed to constitute first word lines, the auxiliary gates of the MIS transistors arranged in the first direction are continuously formed to constitute second word lines, an interlayer dielectric film to cover the first word lines and the second word lines is formed, first shunt lines are formed along the first direction on the interlayer dielectric film and contacts the first word lines, and second shunt lines are formed along the first direction on the interlayer dielectric film and contacts the second word lines.
12. The semiconductor memory device according to claim 11 , wherein the first shunt lines and the second shunt lines are formed out of the same material.
13. The semiconductor memory device according to claim 11 , wherein the first shunt lines and the second shunt lines are formed out of different materials.
14. The semiconductor memory device according to claim 1 , wherein the main gate and the auxiliary gate are formed out of the same material and driven synchronously at different potentials.
15. The semiconductor memory device according to claim 14 , comprising: a row decoder which decodes an inputted row address signal and outputs a decode result signal indicating whether a row address of the row address signal coincides or not, the decode result signal having a first control potential or a second control potential higher than the first control potential based on its decode result; a first output circuit to which the decode result signal is inputted and which outputs a third control potential lower than the first control potential or a fourth control potential higher than the second control potential to the main gate based on the decode result indicated by the decode result signal; and a second output circuit to which the decode result signal is inputted and which outputs a fifth control potential lower than the third control potential or a sixth control potential lower than the fourth control potential to the auxiliary gate based on the decode result indicated by the decode result signal.
16. The semiconductor memory device according to claim 15 , wherein the MIS transistors are arranged in a matrix form to constitute a memory cell array, the memory cell array has first word lines formed along a first direction and second word lines formed along the first direction to make pairs with the first word lines, the main gates of the MIS transistors arranged in the first direction are respectively connected to one of the first word lines, the auxiliary gates of the MIS transistors arranged in the first direction are respectively connected to one of the second word lines, the row decoders, the first output circuits, and the second output circuits for the first and second word lines which make pairs at odd number positions are provided on one side of the memory cell array, and the row decoders, the first output circuits, and the second output circuits for the first and second word lines which makes pairs at even number positions are provided on the other side of the memory cell array.
17. The semiconductor memory device according to claim 15 , wherein the row decoders are provided individually for the first output circuit and the second output circuit.
18. The semiconductor memory device according to claim 17 , wherein the MIS transistors are arranged in a matrix form to constitute a memory cell array, the memory cell array has first word lines formed along a first direction and second word lines formed along the first direction to make pairs with the first word lines, the main gates of the MIS transistors arranged in the first direction are respectively connected to one of the first word lines, the auxiliary gates of the MIS transistors arranged in the first direction are respectively connected to one of the second word lines, the row decoders, the first output circuits, and the second output circuits for the first word lines are provided on one side of the memory cell array, and the row decoders, the first output circuits, and the second output circuits for the second word lines are provided on the other side of the memory cell array.
19. The semiconductor memory device according to claim 1 , wherein the main gate and the auxiliary gate are formed out of materials with different work functions and driven at the same potential.
20. The semiconductor memory device according to claim 19 , comprising: a row decoder which decodes an inputted row address signal and outputs a decode result signal indicating whether a row address of the row address signal coincides or not, the decode result signal having a first control potential or a second control potential higher than the first control potential based on its decode result; and an output circuit to which the decode result signal is inputted and which outputs a third control potential lower than the first control potential or a fourth control potential higher than the second control potential to the main gate and the auxiliary gate based on the decode result indicated by the decode result signal.
21. The semiconductor memory device according to claim 20 , wherein the MIS transistors are arranged in a matrix form to constitute a memory cell array, the memory cell array has first word lines formed along a first direction and second word lines formed along the first direction to make pairs with the first word lines, the main gates of the MIS transistors arranged in the first direction are respectively connected to one of the first word lines, the auxiliary gates of the MIS transistors arranged in the first direction are respectively connected to one of the second word lines, and the row decoders and the output circuits for the first and second word lines are provided on one side of the memory cell array.
22. The semiconductor memory device according to claim 20 , wherein the MIS transistors are arranged in a matrix form to constitute a memory cell array, the memory cell array has first word lines formed along a first direction and second word lines formed along the first direction to make pairs with the first word lines, the main gates of the MIS transistors arranged in the first direction are respectively connected to one of the first word lines, the auxiliary gates of the MIS transistors arranged in the first direction are respectively connected to one of the second word lines, the row decoders and the output circuits for the first and second word lines which make pairs at odd number positions are provided on one side of the memory cell array, and the row decoders and the output circuits for the first and second word lines which make pairs at even number positions are provided on the other side of the memory cell array.
23. The semiconductor memory device according to claim 1 , wherein the MIS transistors are n-channel type and arranged in a matrix form, the drain regions of the MIS transistors arranged in a first direction are respectively connected to one of bit lines, the main gates of the MIS transistors arranged in a second direction are respectively connected to one of first word lines, the auxiliary gates of the MIS transistors arranged in the second direction are respectively connected to one of second word lines, and the source regions of the MIS transistors are connected to a fixed potential line to thereby constitute a memory cell array, wherein at the time of a data write operation, with the fixed potential line as a reference potential, a first control potential higher than the reference potential is applied to a selected first word line, a second control potential lower than the reference potential is applied to non-selected first word lines, a third control potential higher than the reference potential and a fourth control potential lower than the reference potential are applied to the bit line according to the first and second data states, a fifth control potential lower than the first control potential is applied to a second word line selected simultaneously with the first word line, and a six control potential lower than the second control potential is applied to non-selected second word lines.
24. The semiconductor memory device according to claim 1 , wherein the MIS transistors are p-channel type and arranged in a matrix form, the drain regions of the MIS transistors arranged in a first direction are respectively connected to one of bit lines, the main gates of the MIS transistors arranged in a second direction are respectively connected to one of first word lines, the auxiliary gates of the MIS transistors arranged in the second direction are respectively connected to one of second word lines, and the source regions of the MIS transistors are connected to a fixed potential line to thereby constitute a memory cell array, wherein at the time of a data write operation, with the fixed potential line as a reference potential, a first control potential lower than the reference potential is applied to a selected first word line, a second control potential higher than the reference potential is applied to non-selected first word lines, a third control potential lower than the reference potential and a fourth control potential higher than the reference potential are applied to the bit line according to the first and second data states, a fifth control potential higher than the first control potential is applied to a second word line selected simultaneously with the first word line, and a six control potential higher than the second control potential is applied to non-selected second word lines.
25. A semiconductor memory device having MIS transistors to constitute memory cells, each of the MIS transistors having a first data state and a second data state, the semiconductor memory device, comprising: a first semiconductor substrate; auxiliary gates of the MIS transistors formed on the first semiconductor substrate to continue in one direction while their bottom faces and side faces are covered with an insulating film; a second semiconductor substrate provided on the auxiliary gates with a first gate insulating film therebetween; main gates of the MIS transistors formed on the second semiconductor substrate with a second gate insulating film to continue in parallel with the auxiliary gates; source regions formed in space portions between the main gates and the auxiliary gates in the second semiconductor substrate; drain regions formed apart from the source regions in space portions between the main gates and the auxiliary gates in the second semiconductor substrate; source lines provided to be in contact with the source regions and continue in parallel with the main gates and the auxiliary gates; an interlayer dielectric film covering the source lines; and bit lines formed on the interlayer dielectric film in a direction intersecting the main gates and the auxiliary gates and being in contact with the drain regions.
26. The semiconductor memory device according to claim 25 , wherein the second semiconductor substrate is bonded to the first gate insulating film.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
November 9, 2001
August 17, 2004
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