Symmetric multiprocessor systems with an independent super-coherent cache directory

1. A multiprocessor data processing system comprising: a first and second processor having an associated first and second cache, respectively, with shared cache lines; coupling means for interconnecting said first and second processor; a main cache directory affiliated with said first processor and said first cache; and a secondary cache directory of said first cache, which contains a subset of cache line addresses from said main cache directory corresponding to cache lines that are in a first or second coherency state, wherein said second coherency state indicates to said first processor that requests issued from said first processor for a cache line whose address is within said secondary directory should utilized data currently available in said first cache and should not be issued on said coupling means.

2. The data processing system of claim 1 , further comprising: means for snooping a request for data held within a shared cache line on a system bus of said data processing system, wherein said request is issued by a requesting processor and is snooped by a second processor of said data processing system whose cache contains an updated copy of said shared cache line; means, responsive to said snooping of said request by said second processor, for issuing a first response on said system bus indicating to the requesting processor that said requesting processor may utilize data currently stored within the shared cache line of a cache of said requesting processor.

3. The data processing system of claim 2 , further comprising: control logic for forwarding said cache line address in said first coherency state to said secondary directory.

4. The data processing system of claim 3 , further comprising: control logic for directing a transition from said first coherency state to said second coherency state.

5. The data processing system of claim 4 , further comprising: a coherency protocol that directs a transition from said first coherency state and said second coherency state to other coherency states defined within said protocol.

6. The data processing system of claim 5 , further comprising: means, responsive to a receipt of a predetermined condition, for changing said second coherency state to a third coherency state that indicates that said cache line is not valid.

7. The data processing system of claim 4 , further comprising: a clear on barrier flag (COBF) associated with said secondary directory; means for setting said COBF whenever an operation of said first processor is issued to said system bus; and means, responsive to a receipt of a barrier instruction at said first processor when said COBF is set, for dynamically flushing all contents of said secondary directory.

8. The data processing system of claim 1 , further comprising: means for setting a cache line of a first processor to a first coherency state that indicates that modification of data within a shared cache line of a second cache of a second processor has been snooped on a system bus of said data processing system; means for issuing a request for said cache line as a Z 1 read on a system bus, responsive to said cache line being in said first coherency state; means, responsive to a response indicating that said first processor should utilize data currently available within said cache line, for changing said first coherency state to said second coherency state that indicates to said first processor that subsequent request for said cache line should utilize the data within the cache and not be sent to said system bus; and means for providing said request with data of said cache line when said cache line indicates said second coherency state.

9. The data processing of claim 8 , further comprising: means, responsive to a subsequent request for said cache line when said cache line is in said second coherency state, for immediately providing said data within said cache line to said processor.

10. The data processing system of claim 9 , further comprising: means for monitoring a response to said request; and means, when said response indicates that said first processor should utilize new data and that a lock has been acquired for the cache line, for: retrying said Z 1 read until said shared cache line is provided to said first processor from said second processor; and changing said first coherency state to a fourth coherency state when said data is provided to said first processor.

11. The data processing system of claim 1 , further comprising means for removing said cache line address from within said secondary directory when said cache line is no longer in said first or second coherency state.

12. The data processing system of claim 11 , further comprising a logic component that removes a first entered cache line address out of said secondary directory when a new cache line address is received at said secondary directory while said secondary directory is full.