Techniques of shallow trench isolation and devices produced therefrom. The techniques of shallow trench isolation utilize foamed polymers, cured aerogels or air gaps as the insulation medium. Such techniques facilitate lower dielectric constants than the standard silicon dioxide due to the cells of gaseous components inherent in foamed polymers, cured aerogels or air gaps. Lower dielectric constants reduce capacitive coupling concerns and thus permit higher device density in an integrated circuit device.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory device, comprising: an array of memory cells, wherein each memory cell has an access transistor, and wherein a first access transistor of a first memory cell is isolated from a second access transistor of a second memory cell by an interposing trench, and further wherein the trench contains cells of gaseous components; a row access circuit coupled to the array of memory cells; a column access circuit coupled to the array of memory cells; and an address decoder circuit coupled to the row access circuit and the column access circuit.
2. The memory device of claim 1 , wherein the trench contains a fill material selected from the group consisting of a foamed polymeric material, a cured aerogel and an air gap.
3. The memory device of claim 2 , wherein the foamed polymeric material comprises a polymeric material selected from the group consisting of methylsilsesquioxane, polyimides and polynorbornenes.
4. The memory device of claim 2 , wherein the foamed polymeric material comprises a polymeric material selected from the group consisting of Type I and Type III polyimides.
5. A memory device, comprising: an array of memory cells, wherein each memory cell has an access transistor, and wherein a first access transistor of a first memory cell is isolated from a second access transistor of a second memory cell by an interposing trench, and further wherein the trench is filled with a foamed polymeric material; a row access circuit coupled to the array of memory cells; a column access circuit coupled to the array of memory cells; and an address decoder circuit coupled to the row access circuit and the column access circuit.
6. The memory device of claim 5 , further including a metal interconnect structure electrically in communication with a selected number of the array of memory cells.
7. The memory device of claim 6 , wherein the metal interconnect structure includes a refractory metal.
8. The memory device of claim 6 , wherein the metal interconnect structure includes tungsten.
9. The memory device of claim 5 , wherein the a foamed polymeric material includes an elastic modulus of less than about 1.4 GPa and a coefficient of thermal expansion of about 20 m/m C.
10. The memory device of claim 5 , wherein the a foamed polymeric material includes an elastic modulus of less than about 2.4 GPa and a coefficient of thermal expansion of about 40 m/m C.
11. A memory device, comprising: an array of memory cells, wherein each memory cell has an access transistor, and wherein a first access transistor of a first memory cell is isolated from a second access transistor of a second memory cell by an interposing trench, and further wherein the trench is filled with a cured aerogel; a row access circuit coupled to the array of memory cells; a column access circuit coupled to the array of memory cells; and an address decoder circuit coupled to the row access circuit and the column access circuit.
12. The memory device of claim 11 , wherein the cured aerogel includes a silica aerogel.
13. The memory device of claim 11 , wherein the cured aerogel includes a methylsilsesquioxane (MSSQ) material.
14. A memory device, comprising: an array of memory cells, wherein each memory cell has an access transistor, and wherein a first access transistor of a first memory cell is isolated from a second access transistor of a second memory cell by an interposing trench, and further wherein the trench is filled with an air gap; a row access circuit coupled to the array of memory cells; a column access circuit coupled to the array of memory cells; and an address decoder circuit coupled to the row access circuit and the column access circuit.
15. The memory device of claim 14 , further including a metal interconnect structure electrically in communication with a selected number of the array of memory cells.
16. The memory device of claim 15 , wherein the metal interconnect structure includes a refractory metal.
17. The memory device of claim 15 , wherein the metal interconnect structure includes tungsten.
18. A memory module, comprising: a support; a plurality of leads extending from the support; a command link coupled to at least one of the plurality of leads; a plurality of data links, wherein each data link is coupled to at least one of the plurality of leads; and at least one memory device contained on the support and coupled to the command link, wherein the at least one memory device comprises: an array of memory cells, wherein each memory cell has an access transistor, and wherein a first access transistor of a first memory cell is isolated from a second access transistor of a second memory cell by an interposing trench, and further wherein the trench contains cells of gaseous components; a row access circuit coupled to the array of memory cells; a column access circuit coupled to the array of memory cells; and an address decoder circuit coupled to the row access circuit and the column access circuit.
19. The memory module of claim 18 , wherein the trench contains a fill material selected from the group consisting of a foamed polymeric material, a cured aerogel and an air gap.
20. The memory module of claim 19 , wherein the foamed polymeric material comprises a polymeric material selected from the group consisting of methylsilsesquioxane, polyimides and polynorbornenes.
21. The memory module of claim 19 , wherein the foamed polymeric material comprises a polymeric material selected from the group consisting of Type I and Type III polyimides.
22. A memory module, comprising: a support; a plurality of leads extending from the support; a command link coupled to at least one of the plurality of leads; a plurality of data links, wherein each data link is coupled to at least one of the plurality of leads; and at least one memory device contained on the support and coupled to the command link, wherein the at least one memory device comprises: an array of memory cells, wherein each memory cell has an access transistor, and wherein a first access transistor of a first memory cell is isolated from a second access transistor of a second memory cell by an interposing trench, and further wherein the trench is filled with a foamed polymeric material; a row access circuit coupled to the array of memory cells; a column access circuit coupled to the array of memory cells; and an address decoder circuit coupled to the row access circuit and the column access circuit.
23. The memory module of claim 22 , further including a metal interconnect structure electrically in communication with a selected number of the array of memory cells.
24. The memory module of claim 23 , wherein the metal interconnect structure includes a refractory metal.
25. The memory module of claim 23 , wherein the metal interconnect structure includes tungsten.
26. A memory module, comprising: a support; a plurality of leads extending from the support; a command link coupled to at least one of the plurality of leads; a plurality of data links, wherein each data link is coupled to at least one of the plurality of leads; and at least one memory device contained on the support and coupled to the command link, wherein the at least one memory device comprises: an array of memory cells, wherein each memory cell has an access transistor, and wherein a first access transistor of a first memory cell is isolated from a second access transistor of a second memory cell by an interposing trench, and further wherein the trench is filled with a cured aerogel; a row access circuit coupled to the array of memory cells; a column access circuit coupled to the array of memory cells; and an address decoder circuit coupled to the row access circuit and the column access circuit.
27. The memory module of claim 26 , wherein the cured aerogel includes a silica aerogel.
28. The memory module of claim 26 , wherein the cured aerogel includes a methylsilsesquioxane (MSSQ) material.
29. A memory module, comprising: a support; a plurality of leads extending from the support; a command link coupled to at least one of the plurality of leads; a plurality of data links, wherein each data link is coupled to at least one of the plurality of leads; and at least one memory device contained on the support and coupled to the command link, wherein the at least one memory device comprises: an array of memory cells, wherein each memory cell has an access transistor, and wherein a first access transistor of a first memory cell is isolated from a second access transistor of a second memory cell by an interposing trench, and further wherein the trench is filled with an air gap; a row access circuit coupled to the array of memory cells; a column access circuit coupled to the array of memory cells; and an address decoder circuit coupled to the row access circuit and the column access circuit.
30. The memory module of claim 29 , further including a metal interconnect structure electrically in communication with a selected number of the array of memory cells.
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June 27, 2002
August 24, 2004
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