Semiconductor memory device

1. A semiconductor memory device comprising: a main wordline; a plurality of sub-wordlines corresponding to the main wordline; a plurality of main memory cells each being coupled to one of the sub-wordlines; a sub-wordline selector for activating at least one of the sub-wordlines based on a first external address; a main wordline selector for activating the main wordline based on a second external address; at least one redundancy main wordline; a plurality of redundancy sub-wordlines corresponding to the redundancy main wordline; a plurality of redundancy memory cells each being coupled to one of the redundancy sub-wordlines; and a redundancy control circuit for disabling the main wordline selector when among the sub-wordlines, a sub-wordline to which a defective memory cell is coupled is addressed, and for controlling the sub-wordline to be replaced by the redundancy main wordline, wherein the number of the redundancy sub-wordlines coupled to the redundancy main wordline is smaller than the number of the sub-wordlines coupled to the main wordline; and wherein the redundancy control circuit enables the main wordline and sub-wordline selectors when among the sub-wordlines, a sub-wordline to which a normal main memory cell is coupled is addressed.

2. The semiconductor memory device of claim 1 , wherein the redundancy control circuit includes at least one fuse circuit for storing a row address of the defective main memory cell, comparing the stored address with an externally inputted address, and activating a redundancy enable signal when the stored address and the externally inputted address match each other.

3. The semiconductor memory device of claim 2 , wherein the main wordline and sub-wordline selectors are enabled when the redundancy enable signal is inactive, and are disabled when the redundancy enable signal is active.

4. The semiconductor memory device of claim 2 , wherein the redundancy control circuit further includes: a plurality of redundancy sub-row decoders for coupling each of the redundancy sub-wordlines to each of the redundancy main wordlines; and a redundancy predecoder for activating one of the redundancy sub-row decoders based on a part of the first external address when the redundancy enable signal is active.

5. The semiconductor memory device of claim 1 , further comprising a second main wordline.

6. The semiconductor memory device of claim 5 , further comprising: a second plurality of sub-wordlines corresponding to the second main wordline; a second plurality of main memory cells each being coupled to one of the second sub-wordlines; a second sub-wordline selector for activating at least one of the second sub-wordlines based on the first external address.

7. A semiconductor memory device comprising: a main wordline; a plurality of sub-wordlines corresponding to the main wordline; a plurality of main memory cells each being coupled to each of the sub-wordlines; a sub-wordline selector for activating at least one of the sub-wordlines based on a first external address; a main wordline selector for activating the main wordline based on a second external address; at least one redundancy main wordline; a plurality of redundancy sub-wordlines corresponding to the redundancy main wordline; a plurality of redundancy memory cells each being coupled to each of the redundancy sub-wordlines; and a redundancy control circuit for disabling the main wordline selector when among the sub-wordlines, a sub-wordline to which a defective memory cell is coupled is addressed, and for controlling the sub-wordline to be replaced by the redundancy main wordline, wherein the number of the redundancy sub-wordlines coupled to the redundancy wordline is smaller than the number of the sub-wordlines coupled to the main wordline; wherein the redundancy control circuit enables the main wordline and sub-wordline selectors when among the sub-wordlines, a sub-wordline to which a normal main memory cell is coupled is addressed; and wherein the redundancy control circuit includes, at least one fuse circuit for storing a row address of the defective main memory cell, comparing the stored address with an externally inputted address, and activating a redundancy enable signal when the stored address and the externally inputted address match each other, a plurality of sub-row decoders for coupling each of the redundancy sub-wordlines to each of the redundancy main wordlines, and a redundancy predecoder for activating one of the row redundancy sub-row decoders based on a part of the first external address when the redundancy enable signal is active.

8. The semiconductor memory device of claim 7 , further comprising a second main wordline.

9. The semiconductor memory device of claim 8 , further comprising: a second plurality of sub-wordlines corresponding to the second main wordline; a second plurality of main memory cells each being coupled to one of the second sub-wordlines; a second sub-wordline selector for activating at least one of the second sub-wordlines based on the first external address.