A circuit configuration has a transmitter unit connected to a first signal line and a receiver unit connected to a second signal line and is coupled to the transmission unit via a third signal line and a control line. The transmission unit receives and transmits a first bit group to be transmitted and a subsequent, second bit group to be transmitted. The transmission unit respectively identifies a signal state change between bits in the transmitted first bit group and corresponding bits in the received second bit group and determines the number of signal state changes. On the basis of the number thereof, the transmission unit transmits the second bit group to the receiver unit in unaltered or altered form, with altered transmission being indicated by a control signal. By influencing the number of charge reversal operations during signal transmission, the circuit configuration permits an overall reduction in current drawn.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A circuit configuration, comprising: a first signal line and a second signal line for serially transmitting a number of a plurality of bit groups; a transmission unit connected to said first signal line; a third signal line; a control line; and a receiver unit connected to said second signal line and coupled to said transmission unit through said third signal line and said control line; said transmission unit receiving a received first bit group to be transmitted and a subsequent, received second bit group to be transmitted and respectively transmits the received first bit group and the received second bit group to said receiver unit in one of an unaltered and an altered form resulting in a transmitted first bit group and a transmitted second bit group; said transmission unit respectively identifying a signal state change between bits in the transmitted first bit group and corresponding bits in the received second bit group and determines a number of signal state changes; said transmission unit transmitting the received second bit group to said receiver unit in one of an unaltered and an altered form on a basis of the number of signal state changes, with altered transmission being indicated by a control signal on said control line.
2. The circuit configuration according to claim 1 , wherein the bits in the received second bit group received by said transmission unit are transmitted to said receiver unit in inverted form during an altered transmission.
3. The circuit configuration according to claim 1 , wherein said transmission unit determines the number of signal state changes from 0 to 1 between the bits in the transmitted first bit group and the corresponding bits in the received second bit group.
4. The circuit configuration according to claim 3 , wherein said transmission unit transmits the received second bit group to said receiver unit in altered form if the number of signal state changes from 0 to 1 is greater than a number of common corresponding bits in the transmitted first bit group and the received second bit group with state 0.
5. The circuit configuration according to claim 4 , wherein said transmission unit transmits the second bit group to said receiver unit in unaltered form if the number of signal state changes from 0 to 1 is less than or equal to the number of common corresponding bits in the transmitted first bit group and the received second bit group with the state 0.
6. The circuit configuration according to claim 1 , further comprising: a first chip, and said transmission unit is disposed on said first chip; and a second chip, and said receiver unit is disposed on said second chip, said third signal line connecting said first chip to said second chip.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
April 16, 2003
September 14, 2004
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