A process is described for transferring a photoresist pattern into a substrate. In one embodiment a stack comprised of a top photoresist layer, a middle ARC layer, and a bottom hardmask is formed over a gate electrode layer. A line in the photoresist pattern is anisotropically transferred through the ARC and hardmask. Then an isotropic etch to trim the linewidth by 0 to 50 nm per edge is performed simultaneously on the photoresist, ARC and hardmask. This method minimizes the amount of line end shortening to less than three times the dimension trimmed from one line edge. Since a majority of the photoresist layer is retained, the starting photoresist thickness can be reduced by 1000 Angstroms or more to increase process window. The pattern is then etched through the underlying layer to form a gate electrode. The method can also be used to form STI features in a substrate.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for patterning a gate electrode comprising: (a) providing a substrate with a dielectric layer deposited thereon; (b) forming a gate electrode layer on said dielectric layer; (c) forming a hardmask layer on the gate electrode layer and a photosensitive layer on said hardmask layer; (d) patterning said photosensitive layer; (e) etching said hardmask layer; (g) trimming said patterned photosensitive layer and said hardmask layer simultaneously with a plasma etch to form a trimmed pattern; and (h) etching said trimmed pattern through said gate electrode layer.
2. The method of claim 1 wherein the gate electrode is formed between two isolation regions comprising shallow trench isolation (STI) features.
3. The method of claim 1 wherein said dielectric layer is comprised of silicon nitride, silicon oxide, or silicon carbide.
4. The method of claim 1 wherein the gate electrode layer is polysilicon.
5. The method of claim 1 wherein the hardmask layer is silicon nitride or silicon oxynitride with a thickness of about 300 to 1000 Angstroms.
6. The method of claim 1 further comprised of forming an anti-reflective layer (ARC) between said hardmask layer and said photosensitive layer.
7. The method of claim 6 wherein the ARC is an organic or inorganic layer having a thickness between about 300 and 1000 Angstroms.
8. The method of claim 1 wherein said photosensitive layer is a photoresist with a thickness between about 1500 and 4000 Angstroms.
9. The method of claim 1 wherein said pattern comprises a line having a linewidth less than about 200 nm.
10. The method of claim 1 wherein said hardmask layer is etched with conditions comprising a CF 4 flow rate of from about 50 to 200 sccm, an argon flow rate of about 50 to 300 sccm, a chamber pressure of about 5 to 20 mTorr, a chamber temperature of about 50 C. to 70 C. and a RF power between about 200 and 600 Watts.
11. The method of claim 1 wherein the hardmask layer is trimmed with an etch performed with conditions comprising a C X F Y gas flow rate of from 50 to 200 sccm, a H 2 flow rate of 50 to 200 sccm, a chamber pressure of about 5 to 20 mTorr, a chamber temperature of about 50 C. to 70 C., and a RF power of between 300 and 1000 Watts.
12. The method of claim 11 further comprising an O 2 flow rate of from about 5 to 50 sccm.
13. The method of claim 11 wherein said C X F Y gas is selected from a group including CF 4 , C 2 F 6 , C 3 F 6 , C 4 F 6 , C 4 F 8 , and C 5 F 8 .
14. The method of claim 11 wherein the amount of trimming ranges from 0 to about 50 nm per line edge or a total linewidth reduction of 0 to about 100 nm.
15. The method of claim 11 wherein the line end shortening is less than 3 times the dimension that is trimmed from one edge of said line.
16. The method of claim 1 wherein a majority of the original photosensitive layer thickness is retained after said hardmask trim etch.
17. The method of claim 1 wherein said hardmask etch and hardmask trim steps are performed in the same etch chamber.
18. The method of claim 6 wherein said photosensitive layer and ARC are removed before said gate electrode etch.
19. The method of claim 1 further comprising forming spacers on said gate electrode, forming source/drain regions, and forming silicide contacts to fabricate a MOSFET device.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
October 31, 2002
September 21, 2004
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